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mt7603: rename MT_PSE_RESET register

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It is actually a dummy control register used for communicating reset
state with the MCU firmware

Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2017-12-03 21:45:43 +01:00
parent e7eaa7c09b
commit ea4c2a165a
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
mt7603_mac.c
+7 -7
View File
@@ -1066,14 +1066,14 @@ static void mt7603_pse_reset(struct mt7603_dev *dev)
u32 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
/* Reset PSE */
mt76_clear(dev, MT_PSE_RESET, MT_PSE_RESET_SW_S);
mt76_set(dev, MT_PSE_RESET, MT_PSE_RESET_SW);
if (!mt76_poll_msec(dev, MT_PSE_RESET, MT_PSE_RESET_SW_S,
MT_PSE_RESET_SW_S, 500)) {
mt76_clear(dev, MT_PSE_RESET, MT_PSE_RESET_SW);
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S,
MT_MCU_DEBUG_RESET_PSE_S, 500)) {
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
goto out;
}
mt76_clear(dev, MT_PSE_RESET, MT_PSE_RESET_SW_S);
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
mt76_set(dev, addr + MT_CLIENT_RESET_TX, MT_CLIENT_RESET_TX_R_E_1);
mt76_poll_msec(dev, addr + MT_CLIENT_RESET_TX,
@@ -1090,7 +1090,7 @@ static void mt7603_pse_reset(struct mt7603_dev *dev)
mt76_clear(dev, addr + MT_CLIENT_RESET_TX,
MT_CLIENT_RESET_TX_R_E_1 | MT_CLIENT_RESET_TX_R_E_2);
out:
mt76_clear(dev, MT_PSE_RESET, MT_PSE_RESET_QUEUES);
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
}
void mt7603_mac_dma_start(struct mt7603_dev *dev)
mt7603_regs.h
+4 -4
View File
@@ -103,10 +103,10 @@
#define MT_PSE_BASE 0x8000
#define MT_PSE(ofs) (MT_PSE_BASE + (ofs))
#define MT_PSE_RESET MT_PSE(0x16c)
#define MT_PSE_RESET_SW BIT(0)
#define MT_PSE_RESET_SW_S BIT(1)
#define MT_PSE_RESET_QUEUES GENMASK(6, 2)
#define MT_MCU_DEBUG_RESET MT_PSE(0x16c)
#define MT_MCU_DEBUG_RESET_PSE BIT(0)
#define MT_MCU_DEBUG_RESET_PSE_S BIT(1)
#define MT_MCU_DEBUG_RESET_QUEUES GENMASK(6, 2)
#define MT_PSE_FC_P0 MT_PSE(0x120)
#define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0)