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mt7603: adjust timing registers

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2016-02-06 19:06:53 +01:00
parent 102597868e
commit e70b2f8281
4 changed files with 25 additions and 0 deletions
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mt7603.h
+3
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@@ -99,6 +99,8 @@ struct mt7603_dev {
u8 rssi_offset[3];
s16 coverage_class;
struct mt7603_mcu mcu;
struct mt76_queue q_rx;
@@ -151,6 +153,7 @@ static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)
void mt7603_mac_start(struct mt7603_dev *dev);
void mt7603_mac_stop(struct mt7603_dev *dev);
void mt7603_mac_set_timing(struct mt7603_dev *dev);
int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);
void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);
struct sk_buff *mt7603_mac_status_skb(struct mt7603_dev *dev,
mt7603_mac.c
+14
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@@ -41,6 +41,20 @@ mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
}
void mt7603_mac_set_timing(struct mt7603_dev *dev)
{
u32 cck = MT76_SET(MT_TIMEOUT_VAL_PLCP, 231) |
MT76_SET(MT_TIMEOUT_VAL_CCA, 48);
u32 ofdm = MT76_SET(MT_TIMEOUT_VAL_PLCP, 60) |
MT76_SET(MT_TIMEOUT_VAL_CCA, 24);
int offset = 3 * dev->coverage_class;
u32 reg_offset = MT76_SET(MT_TIMEOUT_VAL_PLCP, offset) |
MT76_SET(MT_TIMEOUT_VAL_CCA, offset);
mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
}
static void
mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
{
mt7603_main.c
+3
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@@ -369,6 +369,9 @@ mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
static void mt7603_set_coverage_class(struct ieee80211_hw *hw,
s16 coverage_class)
{
struct mt7603_dev *dev = hw->priv;
dev->coverage_class = coverage_class;
mt7603_mac_set_timing(dev);
}
static void mt7603_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
mt7603_regs.h
+5
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@@ -217,6 +217,11 @@
#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)
#define MT_WMM_TXOP_MASK GENMASK(15, 0)
#define MT_TIMEOUT_CCK MT_WF_TMAC(0x090)
#define MT_TIMEOUT_OFDM MT_WF_TMAC(0x094)
#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
#define MT_WF_RMAC_BASE 0x21800
#define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs))