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mt7603: clean up TMAC TCR register definition

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2016-02-26 12:35:37 +01:00
parent ce0cb8595b
commit 92ac905d07
2 changed files with 20 additions and 20 deletions
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mt7603_init.c
+1 -1
View File
@@ -166,7 +166,7 @@ mt7603_phy_init(struct mt7603_dev *dev)
(MT76_SET(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
MT76_SET(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
mt76_rmw_field(dev, MT_WF_TMAC_TCR, MT_WF_TMAC_TCR_TX_STREAMS,
mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
tx_chains);
}
mt7603_regs.h
+19 -19
View File
@@ -260,25 +260,25 @@ enum {
#define MT_WF_TMAC_BASE 0x21600
#define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs))
#define MT_WF_TMAC_TCR MT_WF_TMAC(0x000)
#define MT_WF_TMAC_TCR_BLINK_SEL GENMASK(7, 6)
#define MT_WF_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8)
#define MT_WF_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)
#define MT_WF_TMAC_TCR_RTS_SIGTA BIT(14)
#define MT_WF_TMAC_TCR_LDPC_OFS BIT(15)
#define MT_WF_TMAC_TCR_TX_STREAMS GENMASK(17, 16)
#define MT_WF_TMAC_SCH_IDLE_SEL GENMASK(19, 18)
#define MT_WF_TMAC_SCH_DET_PER_IOD BIT(20)
#define MT_WF_TMAC_DCH_DET_DISABLE BIT(21)
#define MT_WF_TMAC_TX_RIFS BIT(22)
#define MT_WF_TMAC_RX_RIFS_MODE BIT(23)
#define MT_WF_TMAC_TXOP_TBTT_CONTROL BIT(24)
#define MT_WF_TMAC_TBTT_TX_STOP_CONTROL BIT(25)
#define MT_WF_TMAC_TXOP_BURST_STOP BIT(26)
#define MT_WF_TMAC_RDG_RA_MODE BIT(27)
#define MT_WF_TMAC_RDG_RESP BIT(29)
#define MT_WF_TMAC_RDG_GRANT_NO_PENDING BIT(30)
#define MT_WF_TMAC_SMOOTHING BIT(31)
#define MT_TMAC_TCR MT_WF_TMAC(0x000)
#define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6)
#define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8)
#define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)
#define MT_TMAC_TCR_RTS_SIGTA BIT(14)
#define MT_TMAC_TCR_LDPC_OFS BIT(15)
#define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16)
#define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18)
#define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20)
#define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21)
#define MT_TMAC_TCR_TX_RIFS BIT(22)
#define MT_TMAC_TCR_RX_RIFS_MODE BIT(23)
#define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24)
#define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25)
#define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26)
#define MT_TMAC_TCR_RDG_RA_MODE BIT(27)
#define MT_TMAC_TCR_RDG_RESP BIT(29)
#define MT_TMAC_TCR_RDG_NO_PENDING BIT(30)
#define MT_TMAC_TCR_SMOOTHING BIT(31)
#define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010)
#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))