From 92ac905d0788ec8e350b2dcd08477a734a2a2e58 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 26 Feb 2016 12:35:37 +0100 Subject: [PATCH] mt7603: clean up TMAC TCR register definition Signed-off-by: Felix Fietkau --- mt7603_init.c | 2 +- mt7603_regs.h | 38 +++++++++++++++++++------------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/mt7603_init.c b/mt7603_init.c index 4e90fc43..0238897e 100644 --- a/mt7603_init.c +++ b/mt7603_init.c @@ -166,7 +166,7 @@ mt7603_phy_init(struct mt7603_dev *dev) (MT76_SET(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | MT76_SET(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); - mt76_rmw_field(dev, MT_WF_TMAC_TCR, MT_WF_TMAC_TCR_TX_STREAMS, + mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS, tx_chains); } diff --git a/mt7603_regs.h b/mt7603_regs.h index fd201b45..2076b507 100644 --- a/mt7603_regs.h +++ b/mt7603_regs.h @@ -260,25 +260,25 @@ enum { #define MT_WF_TMAC_BASE 0x21600 #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs)) -#define MT_WF_TMAC_TCR MT_WF_TMAC(0x000) -#define MT_WF_TMAC_TCR_BLINK_SEL GENMASK(7, 6) -#define MT_WF_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8) -#define MT_WF_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12) -#define MT_WF_TMAC_TCR_RTS_SIGTA BIT(14) -#define MT_WF_TMAC_TCR_LDPC_OFS BIT(15) -#define MT_WF_TMAC_TCR_TX_STREAMS GENMASK(17, 16) -#define MT_WF_TMAC_SCH_IDLE_SEL GENMASK(19, 18) -#define MT_WF_TMAC_SCH_DET_PER_IOD BIT(20) -#define MT_WF_TMAC_DCH_DET_DISABLE BIT(21) -#define MT_WF_TMAC_TX_RIFS BIT(22) -#define MT_WF_TMAC_RX_RIFS_MODE BIT(23) -#define MT_WF_TMAC_TXOP_TBTT_CONTROL BIT(24) -#define MT_WF_TMAC_TBTT_TX_STOP_CONTROL BIT(25) -#define MT_WF_TMAC_TXOP_BURST_STOP BIT(26) -#define MT_WF_TMAC_RDG_RA_MODE BIT(27) -#define MT_WF_TMAC_RDG_RESP BIT(29) -#define MT_WF_TMAC_RDG_GRANT_NO_PENDING BIT(30) -#define MT_WF_TMAC_SMOOTHING BIT(31) +#define MT_TMAC_TCR MT_WF_TMAC(0x000) +#define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6) +#define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8) +#define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12) +#define MT_TMAC_TCR_RTS_SIGTA BIT(14) +#define MT_TMAC_TCR_LDPC_OFS BIT(15) +#define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16) +#define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18) +#define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20) +#define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21) +#define MT_TMAC_TCR_TX_RIFS BIT(22) +#define MT_TMAC_TCR_RX_RIFS_MODE BIT(23) +#define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24) +#define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25) +#define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26) +#define MT_TMAC_TCR_RDG_RA_MODE BIT(27) +#define MT_TMAC_TCR_RDG_RESP BIT(29) +#define MT_TMAC_TCR_RDG_NO_PENDING BIT(30) +#define MT_TMAC_TCR_SMOOTHING BIT(31) #define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010) #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))