gitops/mt76
1
0
Fork 0
mirror of https://github.com/outbackdingo/mt76.git synced 2026-10-24 13:26:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

mt76: mt76x02: clean up and fix interrupt masking in the irq handler

Browse Source 
Only clear unmasked interrupts. If an interrupt is temporarily masked,
its pending events need to be processed later, even if another interrupt
happened in the mean time.
Disable interrupts in one call before scheduling

Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2020-08-07 22:10:43 +02:00
parent 2fbd6baac1
commit 5ea8b6187d
1 changed files with 11 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
mt76x02_mmio.c
+11 -14
View File
@@ -262,9 +262,10 @@ EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
{
struct mt76x02_dev *dev = dev_instance;
u32 intr;
u32 intr, mask;
intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
intr &= dev->mt76.mmio.irqmask;
mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
@@ -272,17 +273,17 @@ irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
intr &= dev->mt76.mmio.irqmask;
mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
mask |= MT_INT_TX_DONE_ALL;
if (intr & MT_INT_RX_DONE(0)) {
mt76x02_irq_disable(dev, MT_INT_RX_DONE(0));
mt76x02_irq_disable(dev, mask);
if (intr & MT_INT_RX_DONE(0))
napi_schedule(&dev->mt76.napi[0]);
}
if (intr & MT_INT_RX_DONE(1)) {
mt76x02_irq_disable(dev, MT_INT_RX_DONE(1));
if (intr & MT_INT_RX_DONE(1))
napi_schedule(&dev->mt76.napi[1]);
}
if (intr & MT_INT_PRE_TBTT)
tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
@@ -298,15 +299,11 @@ irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
if (intr & MT_INT_TX_STAT)
mt76x02_mac_poll_tx_status(dev, true);
if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL)) {
mt76x02_irq_disable(dev, MT_INT_TX_DONE_ALL);
if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
napi_schedule(&dev->mt76.tx_napi);
}
if (intr & MT_INT_GPTIMER) {
mt76x02_irq_disable(dev, MT_INT_GPTIMER);
if (intr & MT_INT_GPTIMER)
tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
}
return IRQ_HANDLED;
}