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mt76: mt7615: only clear unmasked interrupts in irq tasklet

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If an interrupt is temporarily masked, its pending events need to be processed
later, even if another interrupt happened in the mean time.

Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2020-08-07 22:09:58 +02:00
parent 06f722d804
commit 2fbd6baac1
1 changed files with 8 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
mt7615/mmio.c
+8 -11
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@@ -106,25 +106,24 @@ static void mt7615_irq_tasklet(unsigned long data)
mt76_wr(dev, MT_INT_MASK_CSR, 0);
intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
intr &= dev->mt76.mmio.irqmask;
mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
intr &= dev->mt76.mmio.irqmask;
if (intr & MT_INT_TX_DONE_ALL) {
mask |= intr & MT_INT_RX_DONE_ALL;
if (intr & MT_INT_TX_DONE_ALL)
mask |= MT_INT_TX_DONE_ALL;
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
if (intr & MT_INT_TX_DONE_ALL)
napi_schedule(&dev->mt76.tx_napi);
}
if (intr & MT_INT_RX_DONE(0)) {
mask |= MT_INT_RX_DONE(0);
if (intr & MT_INT_RX_DONE(0))
napi_schedule(&dev->mt76.napi[0]);
}
if (intr & MT_INT_RX_DONE(1)) {
mask |= MT_INT_RX_DONE(1);
if (intr & MT_INT_RX_DONE(1))
napi_schedule(&dev->mt76.napi[1]);
}
if (intr & MT_INT_MCU_CMD) {
u32 val = mt76_rr(dev, MT_MCU_CMD);
@@ -135,8 +134,6 @@ static void mt7615_irq_tasklet(unsigned long data)
wake_up(&dev->reset_wait);
}
}
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
}
static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)