mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
mt7603: fix checkpatch issues
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
+8
-7
@@ -27,8 +27,8 @@ struct beacon_bc_data {
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static void
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mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
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{
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struct mt7603_dev *dev = (struct mt7603_dev *) priv;
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struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
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struct mt7603_dev *dev = (struct mt7603_dev *)priv;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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struct sk_buff *skb = NULL;
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if (!(dev->beacon_mask & BIT(mvif->idx)))
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@@ -39,7 +39,7 @@ mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
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return;
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mt76_dma_tx_queue_skb(&dev->mt76, &dev->mt76.q_tx[MT_TXQ_BEACON], skb,
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&mvif->sta.wcid, NULL);
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&mvif->sta.wcid, NULL);
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}
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static void
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@@ -47,7 +47,7 @@ mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
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{
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struct beacon_bc_data *data = priv;
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struct mt7603_dev *dev = data->dev;
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struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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struct ieee80211_tx_info *info;
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struct sk_buff *skb;
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@@ -78,7 +78,7 @@ void mt7603_tbtt(struct mt7603_dev *dev)
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void mt7603_pre_tbtt_tasklet(unsigned long arg)
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{
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struct mt7603_dev *dev = (struct mt7603_dev *) arg;
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struct mt7603_dev *dev = (struct mt7603_dev *)arg;
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struct mt76_queue *q;
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struct beacon_bc_data data = {};
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struct sk_buff *skb;
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@@ -122,9 +122,10 @@ void mt7603_pre_tbtt_tasklet(unsigned long arg)
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while ((skb = __skb_dequeue(&data.q)) != NULL) {
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_vif *vif = info->control.vif;
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struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
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struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
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mt76_dma_tx_queue_skb(&dev->mt76, q, skb, &mvif->sta.wcid, NULL);
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mt76_dma_tx_queue_skb(&dev->mt76, q, skb, &mvif->sta.wcid,
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NULL);
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}
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mt76_queue_kick(dev, q);
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spin_unlock_bh(&q->lock);
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@@ -31,6 +31,7 @@ void mt7603_set_irq_mask(struct mt7603_dev *dev, u32 clear, u32 set)
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void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
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{
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struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
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mt7603_irq_enable(dev, MT_INT_RX_DONE(q));
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}
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@@ -49,6 +50,7 @@ irqreturn_t mt7603_irq_handler(int irq, void *dev_instance)
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if (intr & MT_INT_MAC_IRQ3) {
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u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3));
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mt76_wr(dev, MT_HW_INT_STATUS(3), hwintr);
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if (hwintr & MT_HW_INT3_PRE_TBTT0)
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tasklet_schedule(&dev->pre_tbtt_tasklet);
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+4
-2
@@ -34,7 +34,8 @@ mt7603_reset_read(struct seq_file *s, void *data)
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if (!reset_cause_str[i])
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continue;
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seq_printf(s, "%20s: %u\n", reset_cause_str[i], dev->reset_cause[i]);
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seq_printf(s, "%20s: %u\n", reset_cause_str[i],
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dev->reset_cause[i]);
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}
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return 0;
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@@ -49,5 +50,6 @@ void mt7603_init_debugfs(struct mt7603_dev *dev)
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return;
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debugfs_create_u32("reset_test", 0600, dir, &dev->reset_test);
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debugfs_create_devm_seqfile(dev->mt76.dev, "reset", dir, mt7603_reset_read);
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debugfs_create_devm_seqfile(dev->mt76.dev, "reset", dir,
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mt7603_reset_read);
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}
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+12
-10
@@ -27,7 +27,8 @@ mt7603_tx_queue_mcu(struct mt7603_dev *dev, enum mt76_txq_id qid,
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struct mt76_queue_buf buf;
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dma_addr_t addr;
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addr = dma_map_single(dev->mt76.dev, skb->data, skb->len, DMA_TO_DEVICE);
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addr = dma_map_single(dev->mt76.dev, skb->data, skb->len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev->mt76.dev, addr))
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return -ENOMEM;
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@@ -43,7 +44,7 @@ mt7603_tx_queue_mcu(struct mt7603_dev *dev, enum mt76_txq_id qid,
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static int
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mt7603_init_tx_queue(struct mt7603_dev *dev, struct mt76_queue *q,
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int idx, int n_desc)
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int idx, int n_desc)
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{
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int ret;
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@@ -64,13 +65,13 @@ void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb)
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{
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struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
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__le32 *rxd = (__le32 *) skb->data;
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__le32 *end = (__le32 *) &skb->data[skb->len];
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__le32 *rxd = (__le32 *)skb->data;
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__le32 *end = (__le32 *)&skb->data[skb->len];
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enum rx_pkt_type type;
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type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
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switch(type) {
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switch (type) {
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case PKT_TYPE_TXS:
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for (rxd++; rxd + 5 <= end; rxd += 5)
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mt7603_mac_add_txs(dev, rxd);
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@@ -93,7 +94,7 @@ void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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static int
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mt7603_init_rx_queue(struct mt7603_dev *dev, struct mt76_queue *q,
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int idx, int n_desc, int bufsize)
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int idx, int n_desc, int bufsize)
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{
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int ret;
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@@ -113,7 +114,7 @@ mt7603_init_rx_queue(struct mt7603_dev *dev, struct mt76_queue *q,
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static void
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mt7603_tx_tasklet(unsigned long data)
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{
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struct mt7603_dev *dev = (struct mt7603_dev *) data;
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struct mt7603_dev *dev = (struct mt7603_dev *)data;
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int i;
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dev->tx_dma_check = 0;
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@@ -139,7 +140,7 @@ int mt7603_dma_init(struct mt7603_dev *dev)
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init_waitqueue_head(&dev->mt76.mmio.mcu.wait);
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skb_queue_head_init(&dev->mt76.mmio.mcu.res_q);
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tasklet_init(&dev->tx_tasklet, mt7603_tx_tasklet, (unsigned long) dev);
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tasklet_init(&dev->tx_tasklet, mt7603_tx_tasklet, (unsigned long)dev);
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mt76_clear(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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@@ -150,8 +151,9 @@ int mt7603_dma_init(struct mt7603_dev *dev)
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
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ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[i], wmm_queue_map[i],
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MT_TX_RING_SIZE);
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ret = mt7603_init_tx_queue(dev, &dev->mt76.q_tx[i],
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wmm_queue_map[i],
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MT_TX_RING_SIZE);
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if (ret)
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return ret;
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}
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+6
-8
@@ -44,8 +44,8 @@ mt7603_efuse_read(struct mt7603_dev *dev, u32 base, u16 addr, u8 *data)
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}
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for (i = 0; i < 4; i++) {
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val = mt76_rr(dev, base + MT_EFUSE_RDATA(i));
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put_unaligned_le32(val, data + 4 * i);
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val = mt76_rr(dev, base + MT_EFUSE_RDATA(i));
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put_unaligned_le32(val, data + 4 * i);
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}
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return 0;
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@@ -101,7 +101,6 @@ mt7603_has_cal_free_data(struct mt7603_dev *dev, u8 *efuse)
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return true;
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}
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static void
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mt7603_apply_cal_free_data(struct mt7603_dev *dev, u8 *efuse)
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{
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@@ -121,18 +120,18 @@ mt7603_apply_cal_free_data(struct mt7603_dev *dev, u8 *efuse)
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int i;
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if (!mt7603_has_cal_free_data(dev, efuse))
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return;
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return;
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if (is_mt7628(dev))
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n -= 2;
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for (i = 0; i < n; i++) {
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int offset = cal_free_bytes[i];
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eeprom[offset] = efuse[offset];
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int offset = cal_free_bytes[i];
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eeprom[offset] = efuse[offset];
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}
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}
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static int
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mt7603_eeprom_load(struct mt7603_dev *dev)
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{
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@@ -158,7 +157,6 @@ static int mt7603_check_eeprom(struct mt76_dev *dev)
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}
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}
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int mt7603_eeprom_init(struct mt7603_dev *dev)
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{
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int ret;
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@@ -54,7 +54,6 @@ enum mt7603_eeprom_field {
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MT_EE_TX_POWER_1_START_5G = 0x080,
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MT_EE_TX_POWER_CCK = 0x0a0,
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MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2,
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MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4,
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+5
-5
@@ -307,14 +307,14 @@ mt7603_init_hardware(struct mt7603_dev *dev)
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#define CCK_RATE(_idx, _rate) { \
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.bitrate = _rate, \
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.flags = IEEE80211_RATE_SHORT_PREAMBLE, \
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.hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
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.hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
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.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
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}
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#define OFDM_RATE(_idx, _rate) { \
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.bitrate = _rate, \
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.hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
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.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
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.hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
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.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
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}
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static struct ieee80211_rate mt7603_rates[] = {
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@@ -413,9 +413,9 @@ int mt7603_register_device(struct mt7603_dev *dev)
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struct wiphy *wiphy = hw->wiphy;
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int ret;
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INIT_DELAYED_WORK(&dev->mac_work, mt7603_mac_work);
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tasklet_init(&dev->pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet, (unsigned long) dev);
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tasklet_init(&dev->pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet,
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(unsigned long)dev);
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dev->rx_chains = 2;
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dev->tx_chains = 2;
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+75
-65
@@ -101,6 +101,7 @@ static u32
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mt7603_wtbl3_addr(int idx)
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{
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u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
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return base + idx * MT_WTBL3_SIZE;
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}
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@@ -108,6 +109,7 @@ static u32
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mt7603_wtbl4_addr(int idx)
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{
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u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
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return base + idx * MT_WTBL4_SIZE;
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}
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@@ -153,10 +155,11 @@ void mt7603_wtbl_set_ps(struct mt7603_dev *dev, int idx, bool enabled)
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{
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u32 addr = mt7603_wtbl1_addr(idx);
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u32 reg = mt76_rr(dev, addr + 3 * 4);
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u32 val = (reg & ~MT_WTBL1_W3_SKIP_TX) | (enabled * MT_WTBL1_W3_SKIP_TX);
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u32 val = (reg & ~MT_WTBL1_W3_SKIP_TX) |
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(enabled * MT_WTBL1_W3_SKIP_TX);
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if (reg == val)
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return;
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return;
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mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
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mt76_wr(dev, addr + 3 * 4, val);
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@@ -223,7 +226,7 @@ void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
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void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
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{
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struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
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struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
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int idx = msta->wcid.idx;
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u32 addr;
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u32 val;
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@@ -378,7 +381,7 @@ mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
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static void
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mt7603_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id)
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{
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struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb;
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struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
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int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
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u8 *pn = status->iv;
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u8 *hdr;
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@@ -402,10 +405,10 @@ mt7603_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id)
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int
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mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
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{
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struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb;
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struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
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struct ieee80211_supported_band *sband;
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struct ieee80211_hdr *hdr;
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__le32 *rxd = (__le32 *) skb->data;
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__le32 *rxd = (__le32 *)skb->data;
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u32 rxd0 = le32_to_cpu(rxd[0]);
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u32 rxd1 = le32_to_cpu(rxd[1]);
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u32 rxd2 = le32_to_cpu(rxd[2]);
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@@ -452,30 +455,30 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
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rxd += 4;
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if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
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rxd += 4;
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if ((u8 *) rxd - skb->data >= skb->len)
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if ((u8 *)rxd - skb->data >= skb->len)
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return -EINVAL;
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}
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if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
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u8 *data = (u8 *) rxd;
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u8 *data = (u8 *)rxd;
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if (status->flag & RX_FLAG_DECRYPTED) {
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status->iv[0] = data[5];
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status->iv[1] = data[4];
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status->iv[2] = data[3];
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status->iv[3] = data[2];
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status->iv[4] = data[1];
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status->iv[5] = data[0];
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status->iv[0] = data[5];
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status->iv[1] = data[4];
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status->iv[2] = data[3];
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status->iv[3] = data[2];
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status->iv[4] = data[1];
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status->iv[5] = data[0];
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insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
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insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
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}
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rxd += 4;
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if ((u8 *) rxd - skb->data >= skb->len)
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if ((u8 *)rxd - skb->data >= skb->len)
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return -EINVAL;
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}
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if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
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rxd += 2;
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if ((u8 *) rxd - skb->data >= skb->len)
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if ((u8 *)rxd - skb->data >= skb->len)
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return -EINVAL;
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}
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if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
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@@ -522,24 +525,26 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
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status->bw = RATE_INFO_BW_40;
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rxd += 6;
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if ((u8 *) rxd - skb->data >= skb->len)
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if ((u8 *)rxd - skb->data >= skb->len)
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return -EINVAL;
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} else {
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return -EINVAL;
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}
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skb_pull(skb, (u8 *) rxd - skb->data + 2 * remove_pad);
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skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
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if (insert_ccmp_hdr) {
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u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
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mt7603_insert_ccmp_hdr(skb, key_id);
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}
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hdr = (struct ieee80211_hdr *) skb->data;
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hdr = (struct ieee80211_hdr *)skb->data;
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if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
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return 0;
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|
||||
status->aggr = unicast && !ieee80211_is_qos_nullfunc(hdr->frame_control);
|
||||
status->aggr = unicast &&
|
||||
!ieee80211_is_qos_nullfunc(hdr->frame_control);
|
||||
status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
|
||||
status->seqno = hdr->seq_ctrl >> 4;
|
||||
|
||||
@@ -690,7 +695,7 @@ mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
|
||||
|
||||
memcpy(key_data, key->key, key->keylen);
|
||||
|
||||
switch(key->cipher) {
|
||||
switch (key->cipher) {
|
||||
case WLAN_CIPHER_SUITE_WEP40:
|
||||
return MT_CIPHER_WEP40;
|
||||
case WLAN_CIPHER_SUITE_WEP104:
|
||||
@@ -740,7 +745,7 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
{
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ieee80211_tx_rate *rate = &info->control.rates[0];
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
|
||||
struct ieee80211_vif *vif = info->control.vif;
|
||||
struct mt7603_vif *mvif;
|
||||
int wlan_idx;
|
||||
@@ -749,17 +754,18 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
u8 frame_type, frame_subtype;
|
||||
u16 fc = le16_to_cpu(hdr->frame_control);
|
||||
u8 vif_idx = 0;
|
||||
u32 val;
|
||||
u8 bw;
|
||||
|
||||
if (vif) {
|
||||
mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
vif_idx = mvif->idx;
|
||||
if (vif_idx && q >= &dev->mt76.q_tx[MT_TXQ_BEACON])
|
||||
vif_idx += 0x10;
|
||||
}
|
||||
|
||||
if (sta) {
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
tx_count = msta->rate_count;
|
||||
}
|
||||
|
||||
@@ -771,38 +777,38 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
|
||||
frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
|
||||
|
||||
txwi[0] = cpu_to_le32(
|
||||
FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
|
||||
FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx)
|
||||
);
|
||||
txwi[1] = cpu_to_le32(
|
||||
MT_TXD1_LONG_FORMAT |
|
||||
FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
|
||||
FIELD_PREP(MT_TXD1_TID, skb->priority &
|
||||
IEEE80211_QOS_CTL_TID_MASK) |
|
||||
FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
|
||||
FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
|
||||
FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
|
||||
FIELD_PREP(MT_TXD1_PROTECTED, !!key)
|
||||
);
|
||||
val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
|
||||
FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
|
||||
txwi[0] = cpu_to_le32(val);
|
||||
|
||||
val = MT_TXD1_LONG_FORMAT |
|
||||
FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
|
||||
FIELD_PREP(MT_TXD1_TID,
|
||||
skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
|
||||
FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
|
||||
FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
|
||||
FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
|
||||
FIELD_PREP(MT_TXD1_PROTECTED, !!key);
|
||||
txwi[1] = cpu_to_le32(val);
|
||||
|
||||
if (info->flags & IEEE80211_TX_CTL_NO_ACK)
|
||||
txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
|
||||
|
||||
txwi[2] = cpu_to_le32(
|
||||
FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
|
||||
FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
|
||||
FIELD_PREP(MT_TXD2_MULTICAST, is_multicast_ether_addr(hdr->addr1))
|
||||
);
|
||||
val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
|
||||
FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
|
||||
FIELD_PREP(MT_TXD2_MULTICAST,
|
||||
is_multicast_ether_addr(hdr->addr1));
|
||||
txwi[2] = cpu_to_le32(val);
|
||||
|
||||
if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
|
||||
txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
|
||||
|
||||
txwi[4] = 0;
|
||||
txwi[5] = cpu_to_le32(
|
||||
MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
|
||||
FIELD_PREP(MT_TXD5_PID, pid)
|
||||
);
|
||||
|
||||
val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
|
||||
FIELD_PREP(MT_TXD5_PID, pid);
|
||||
txwi[5] = cpu_to_le32(val);
|
||||
|
||||
txwi[6] = 0;
|
||||
|
||||
if (rate->idx >= 0 && rate->count &&
|
||||
@@ -810,12 +816,11 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
|
||||
u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
|
||||
|
||||
txwi[6] |= cpu_to_le32(
|
||||
MT_TXD6_FIXED_RATE |
|
||||
MT_TXD6_FIXED_BW |
|
||||
FIELD_PREP(MT_TXD6_BW, bw) |
|
||||
FIELD_PREP(MT_TXD6_TX_RATE, rateval)
|
||||
);
|
||||
val = MT_TXD6_FIXED_RATE |
|
||||
MT_TXD6_FIXED_BW |
|
||||
FIELD_PREP(MT_TXD6_BW, bw) |
|
||||
FIELD_PREP(MT_TXD6_TX_RATE, rateval);
|
||||
txwi[6] |= cpu_to_le32(val);
|
||||
|
||||
if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
|
||||
txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
|
||||
@@ -830,13 +835,13 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
if (q->hw_idx == MT_TX_HW_QUEUE_BCN)
|
||||
tx_count = 0x1f;
|
||||
|
||||
txwi[3] = cpu_to_le32(
|
||||
FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
|
||||
FIELD_PREP(MT_TXD3_SEQ, le16_to_cpu(hdr->seq_ctrl))
|
||||
);
|
||||
val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
|
||||
FIELD_PREP(MT_TXD3_SEQ, le16_to_cpu(hdr->seq_ctrl));
|
||||
txwi[3] = cpu_to_le32(val);
|
||||
|
||||
if (key) {
|
||||
u64 pn = atomic64_inc_return(&key->tx_pn);
|
||||
|
||||
txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
|
||||
txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
|
||||
txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
|
||||
@@ -926,7 +931,8 @@ mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
|
||||
|
||||
if (fixed_rate) {
|
||||
info->status.ampdu_len = 1;
|
||||
info->status.ampdu_ack_len = !!(info->flags & IEEE80211_TX_STAT_ACK);
|
||||
info->status.ampdu_ack_len = !!(info->flags &
|
||||
IEEE80211_TX_STAT_ACK);
|
||||
} else {
|
||||
info->status.ampdu_len = sta->ampdu_count;
|
||||
info->status.ampdu_ack_len = sta->ampdu_acked;
|
||||
@@ -998,7 +1004,8 @@ mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
|
||||
if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
|
||||
spin_lock_bh(&dev->mt76.lock);
|
||||
if (sta->rate_probe) {
|
||||
mt7603_wtbl_set_rates(dev, sta, NULL, sta->rates);
|
||||
mt7603_wtbl_set_rates(dev, sta, NULL,
|
||||
sta->rates);
|
||||
sta->rate_probe = false;
|
||||
}
|
||||
spin_unlock_bh(&dev->mt76.lock);
|
||||
@@ -1092,8 +1099,9 @@ static void mt7603_pse_reset(struct mt7603_dev *dev)
|
||||
MT_MCU_DEBUG_RESET_PSE_S, 500)) {
|
||||
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
|
||||
dev->pse_reset_failed++;
|
||||
} else
|
||||
} else {
|
||||
dev->pse_reset_failed = 0;
|
||||
}
|
||||
|
||||
mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
|
||||
}
|
||||
@@ -1103,7 +1111,7 @@ void mt7603_mac_dma_start(struct mt7603_dev *dev)
|
||||
mt7603_mac_start(dev);
|
||||
|
||||
wait_for_wpdma(dev);
|
||||
udelay(50);
|
||||
usleep_range(50, 100);
|
||||
|
||||
mt76_set(dev, MT_WPDMA_GLO_CFG,
|
||||
(MT_WPDMA_GLO_CFG_TX_DMA_EN |
|
||||
@@ -1152,7 +1160,7 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
|
||||
mt76_clear(dev, MT_WPDMA_GLO_CFG,
|
||||
MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
|
||||
MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
|
||||
msleep(1);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
mt7603_irq_disable(dev, mask);
|
||||
|
||||
@@ -1234,7 +1242,8 @@ static bool mt7603_tx_hang(struct mt7603_dev *dev)
|
||||
continue;
|
||||
|
||||
prev_dma_idx = dev->tx_dma_idx[i];
|
||||
dev->tx_dma_idx[i] = dma_idx = ioread32(&q->regs->dma_idx);
|
||||
dma_idx = ioread32(&q->regs->dma_idx);
|
||||
dev->tx_dma_idx[i] = dma_idx;
|
||||
|
||||
if (dma_idx == prev_dma_idx &&
|
||||
dma_idx != ioread32(&q->regs->cpu_idx))
|
||||
@@ -1310,7 +1319,8 @@ void mt7603_update_channel(struct mt76_dev *mdev)
|
||||
|
||||
void mt7603_mac_work(struct work_struct *work)
|
||||
{
|
||||
struct mt7603_dev *dev = container_of(work, struct mt7603_dev, mac_work.work);
|
||||
struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
|
||||
mac_work.work);
|
||||
bool reset = false;
|
||||
|
||||
mt76_tx_status_check(&dev->mt76, NULL, false);
|
||||
|
||||
+4
-4
@@ -134,10 +134,10 @@ enum rx_pkt_type {
|
||||
#define MT_RXV6_NF0 GENMASK(7, 0)
|
||||
|
||||
enum mt7603_tx_header_format {
|
||||
MT_HDR_FORMAT_802_3,
|
||||
MT_HDR_FORMAT_CMD,
|
||||
MT_HDR_FORMAT_802_11,
|
||||
MT_HDR_FORMAT_802_11_EXT,
|
||||
MT_HDR_FORMAT_802_3,
|
||||
MT_HDR_FORMAT_CMD,
|
||||
MT_HDR_FORMAT_802_11,
|
||||
MT_HDR_FORMAT_802_11_EXT,
|
||||
};
|
||||
|
||||
#define MT_TXD_SIZE (8 * 4)
|
||||
|
||||
+29
-27
@@ -56,10 +56,10 @@ mt7603_txq_init(struct mt7603_dev *dev, struct ieee80211_txq *txq)
|
||||
|
||||
mtxq = (struct mt76_txq *) txq->drv_priv;
|
||||
if (txq->sta) {
|
||||
struct mt7603_sta *sta = (struct mt7603_sta *) txq->sta->drv_priv;
|
||||
struct mt7603_sta *sta = (struct mt7603_sta *)txq->sta->drv_priv;
|
||||
mtxq->wcid = &sta->wcid;
|
||||
} else {
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) txq->vif->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)txq->vif->drv_priv;
|
||||
mtxq->wcid = &mvif->sta.wcid;
|
||||
}
|
||||
|
||||
@@ -69,7 +69,7 @@ mt7603_txq_init(struct mt7603_dev *dev, struct ieee80211_txq *txq)
|
||||
static int
|
||||
mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
u8 bc_addr[ETH_ALEN];
|
||||
int idx;
|
||||
@@ -110,7 +110,7 @@ out:
|
||||
static void
|
||||
mt7603_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
||||
{
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
int idx = mvif->sta.wcid.idx;
|
||||
|
||||
@@ -158,7 +158,8 @@ mt7603_set_channel(struct mt7603_dev *dev, struct cfg80211_chan_def *def)
|
||||
|
||||
memcpy(dev->rssi_offset, rssi_data, sizeof(dev->rssi_offset));
|
||||
|
||||
idx |= (def->chan - mt76_hw(dev)->wiphy->bands[def->chan->band]->channels) << 1;
|
||||
idx |= (def->chan -
|
||||
mt76_hw(dev)->wiphy->bands[def->chan->band]->channels) << 1;
|
||||
mt76_wr(dev, MT_WF_RMAC_CH_FREQ, idx);
|
||||
mt7603_mac_start(dev);
|
||||
mt7603_mac_set_timing(dev);
|
||||
@@ -190,7 +191,6 @@ mt7603_config(struct ieee80211_hw *hw, u32 changed)
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
int ret = 0;
|
||||
|
||||
|
||||
if (changed & IEEE80211_CONF_CHANGE_CHANNEL)
|
||||
ret = mt7603_set_channel(dev, &hw->conf.chandef);
|
||||
|
||||
@@ -207,13 +207,12 @@ mt7603_config(struct ieee80211_hw *hw, u32 changed)
|
||||
mutex_unlock(&dev->mt76.mutex);
|
||||
}
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
mt7603_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
|
||||
unsigned int *total_flags, u64 multicast)
|
||||
unsigned int *total_flags, u64 multicast)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
u32 flags = 0;
|
||||
@@ -256,7 +255,7 @@ mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_bss_conf *info, u32 changed)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
|
||||
mutex_lock(&dev->mt76.mutex);
|
||||
|
||||
@@ -280,6 +279,7 @@ mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
|
||||
if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON_INT)) {
|
||||
int beacon_int = !!info->enable_beacon * info->beacon_int;
|
||||
|
||||
tasklet_disable(&dev->pre_tbtt_tasklet);
|
||||
mt7603_beacon_set_timer(dev, mvif->idx, beacon_int);
|
||||
tasklet_enable(&dev->pre_tbtt_tasklet);
|
||||
@@ -290,11 +290,11 @@ mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
|
||||
static int
|
||||
mt7603_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
int i, idx;
|
||||
int ret = 0;
|
||||
|
||||
@@ -327,10 +327,10 @@ out:
|
||||
|
||||
static int
|
||||
mt7603_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
int idx = msta->wcid.idx;
|
||||
int i;
|
||||
|
||||
@@ -353,7 +353,7 @@ void
|
||||
mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
|
||||
{
|
||||
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
int idx = msta->wcid.idx;
|
||||
|
||||
mt76_stop_tx_queues(&dev->mt76, sta, false);
|
||||
@@ -362,12 +362,12 @@ mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
|
||||
|
||||
static int
|
||||
mt7603_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
||||
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
|
||||
struct ieee80211_key_conf *key)
|
||||
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
|
||||
struct ieee80211_key_conf *key)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *) vif->drv_priv;
|
||||
struct mt7603_sta *msta = sta ? (struct mt7603_sta *) sta->drv_priv :
|
||||
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
|
||||
struct mt7603_sta *msta = sta ? (struct mt7603_sta *)sta->drv_priv :
|
||||
&mvif->sta;
|
||||
struct mt76_wcid *wcid = &msta->wcid;
|
||||
int idx = key->keyidx;
|
||||
@@ -410,7 +410,7 @@ mt7603_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
|
||||
|
||||
static int
|
||||
mt7603_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
|
||||
const struct ieee80211_tx_queue_params *params)
|
||||
const struct ieee80211_tx_queue_params *params)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
u16 cw_min = (1 << 5) - 1;
|
||||
@@ -454,7 +454,8 @@ mt7603_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
|
||||
}
|
||||
|
||||
static void
|
||||
mt7603_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const u8 *mac)
|
||||
mt7603_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
const u8 *mac)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
|
||||
@@ -473,7 +474,7 @@ mt7603_sw_scan_complete(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
|
||||
|
||||
static void
|
||||
mt7603_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
u32 queues, bool drop)
|
||||
u32 queues, bool drop)
|
||||
{
|
||||
}
|
||||
|
||||
@@ -491,7 +492,7 @@ mt7603_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct ieee80211_sta *sta = params->sta;
|
||||
struct ieee80211_txq *txq = sta->txq[params->tid];
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
u16 tid = params->tid;
|
||||
u16 *ssn = ¶ms->ssn;
|
||||
u8 ba_size = params->buf_size;
|
||||
@@ -538,10 +539,10 @@ mt7603_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
|
||||
static void
|
||||
mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *) sta->drv_priv;
|
||||
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
|
||||
struct ieee80211_sta_rates *sta_rates = rcu_dereference(sta->rates);
|
||||
int i;
|
||||
|
||||
@@ -561,9 +562,10 @@ mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
}
|
||||
|
||||
static void mt7603_set_coverage_class(struct ieee80211_hw *hw,
|
||||
s16 coverage_class)
|
||||
s16 coverage_class)
|
||||
{
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
|
||||
dev->coverage_class = coverage_class;
|
||||
mt7603_mac_set_timing(dev);
|
||||
}
|
||||
@@ -571,7 +573,7 @@ static void mt7603_set_coverage_class(struct ieee80211_hw *hw,
|
||||
static void mt7603_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
|
||||
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ieee80211_vif *vif = info->control.vif;
|
||||
struct mt7603_dev *dev = hw->priv;
|
||||
|
||||
+24
-13
@@ -60,7 +60,8 @@ mt7603_mcu_get_response(struct mt7603_dev *dev, unsigned long expires)
|
||||
return NULL;
|
||||
|
||||
timeout = expires - jiffies;
|
||||
wait_event_timeout(mdev->mmio.mcu.wait, !skb_queue_empty(&mdev->mmio.mcu.res_q),
|
||||
wait_event_timeout(mdev->mmio.mcu.wait,
|
||||
!skb_queue_empty(&mdev->mmio.mcu.res_q),
|
||||
timeout);
|
||||
return skb_dequeue(&mdev->mmio.mcu.res_q);
|
||||
}
|
||||
@@ -80,7 +81,7 @@ __mt7603_mcu_msg_send(struct mt7603_dev *dev, struct sk_buff *skb, int cmd, int
|
||||
if (!seq)
|
||||
seq = ++mdev->mmio.mcu.msg_seq & 0xf;
|
||||
|
||||
txd = (struct mt7603_mcu_txd *) skb_push(skb, hdrlen);
|
||||
txd = (struct mt7603_mcu_txd *)skb_push(skb, hdrlen);
|
||||
memset(txd, 0, hdrlen);
|
||||
|
||||
txd->len = cpu_to_le16(skb->len);
|
||||
@@ -126,13 +127,15 @@ mt7603_mcu_msg_send(struct mt7603_dev *dev, struct sk_buff *skb, int cmd, int qu
|
||||
while (1) {
|
||||
skb = mt7603_mcu_get_response(dev, expires);
|
||||
if (!skb) {
|
||||
printk("MCU message %d (seq %d) timed out\n", cmd, seq);
|
||||
dev_err(mdev->dev,
|
||||
"MCU message %d (seq %d) timed out\n",
|
||||
cmd, seq);
|
||||
dev->tx_dma_check = MT7603_WATCHDOG_TIMEOUT;
|
||||
ret = -ETIMEDOUT;
|
||||
break;
|
||||
}
|
||||
|
||||
rxd = (struct mt7603_mcu_rxd *) skb->data;
|
||||
rxd = (struct mt7603_mcu_rxd *)skb->data;
|
||||
skb_pull(skb, sizeof(*rxd));
|
||||
|
||||
if (seq != rxd->seq)
|
||||
@@ -166,7 +169,8 @@ mt7603_mcu_init_download(struct mt7603_dev *dev, u32 addr, u32 len)
|
||||
};
|
||||
struct sk_buff *skb = mt7603_mcu_msg_alloc(&req, sizeof(req));
|
||||
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_TARGET_ADDRESS_LEN_REQ, MCU_Q_NA, NULL);
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_TARGET_ADDRESS_LEN_REQ,
|
||||
MCU_Q_NA, NULL);
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -182,7 +186,8 @@ mt7603_mcu_send_firmware(struct mt7603_dev *dev, const void *data, int len)
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = __mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_SCATTER, MCU_Q_NA, NULL);
|
||||
ret = __mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_SCATTER,
|
||||
MCU_Q_NA, NULL);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
@@ -205,7 +210,8 @@ mt7603_mcu_start_firmware(struct mt7603_dev *dev, u32 addr)
|
||||
};
|
||||
struct sk_buff *skb = mt7603_mcu_msg_alloc(&req, sizeof(req));
|
||||
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_START_REQ, MCU_Q_NA, NULL);
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_FW_START_REQ,
|
||||
MCU_Q_NA, NULL);
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -213,7 +219,8 @@ mt7603_mcu_restart(struct mt7603_dev *dev)
|
||||
{
|
||||
struct sk_buff *skb = mt7603_mcu_msg_alloc(NULL, 0);
|
||||
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_RESTART_DL_REQ, MCU_Q_NA, NULL);
|
||||
return mt7603_mcu_msg_send(dev, skb, -MCU_CMD_RESTART_DL_REQ,
|
||||
MCU_Q_NA, NULL);
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -248,7 +255,8 @@ mt7603_load_firmware(struct mt7603_dev *dev)
|
||||
goto out;
|
||||
}
|
||||
|
||||
hdr = (const struct mt7603_fw_trailer *) (fw->data + fw->size - sizeof(*hdr));
|
||||
hdr = (const struct mt7603_fw_trailer *)(fw->data + fw->size -
|
||||
sizeof(*hdr));
|
||||
|
||||
dev_info(dev->mt76.dev, "Firmware Version: %.10s\n", hdr->fw_ver);
|
||||
dev_info(dev->mt76.dev, "Build Time: %.15s\n", hdr->build_date);
|
||||
@@ -306,7 +314,7 @@ running:
|
||||
mt76_clear(dev, MT_SCH_4, BIT(8));
|
||||
|
||||
dev->mcu_running = true;
|
||||
printk("firmware init done\n");
|
||||
dev_info(dev->mt76.dev, "firmware init done\n");
|
||||
|
||||
out:
|
||||
release_firmware(fw);
|
||||
@@ -317,6 +325,7 @@ out:
|
||||
int mt7603_mcu_init(struct mt7603_dev *dev)
|
||||
{
|
||||
mutex_init(&dev->mt76.mmio.mcu.mutex);
|
||||
|
||||
return mt7603_load_firmware(dev);
|
||||
}
|
||||
|
||||
@@ -440,7 +449,7 @@ static int mt7603_mcu_set_tx_power(struct mt7603_dev *dev)
|
||||
u8 reserved;
|
||||
} req = {
|
||||
.center_channel = dev->mt76.chandef.chan->hw_value,
|
||||
#define EEP_VAL(n) ((u8 *) dev->mt76.eeprom.data)[n]
|
||||
#define EEP_VAL(n) ((u8 *)dev->mt76.eeprom.data)[n]
|
||||
.tssi = EEP_VAL(MT_EE_NIC_CONF_1 + 1),
|
||||
.temp_comp = EEP_VAL(MT_EE_NIC_CONF_1),
|
||||
.target_power = {
|
||||
@@ -468,7 +477,8 @@ static int mt7603_mcu_set_tx_power(struct mt7603_dev *dev)
|
||||
sizeof(req.temp_comp_power));
|
||||
|
||||
skb = mt7603_mcu_msg_alloc(&req, sizeof(req));
|
||||
return mt7603_mcu_msg_send(dev, skb, MCU_EXT_CMD_SET_TX_POWER_CTRL, MCU_Q_SET, NULL);
|
||||
return mt7603_mcu_msg_send(dev, skb, MCU_EXT_CMD_SET_TX_POWER_CTRL,
|
||||
MCU_Q_SET, NULL);
|
||||
}
|
||||
|
||||
int mt7603_mcu_set_channel(struct mt7603_dev *dev)
|
||||
@@ -503,7 +513,8 @@ int mt7603_mcu_set_channel(struct mt7603_dev *dev)
|
||||
|
||||
memset(req.txpower, 0xff, sizeof(req.txpower));
|
||||
skb = mt7603_mcu_msg_alloc(&req, sizeof(req));
|
||||
ret = mt7603_mcu_msg_send(dev, skb, MCU_EXT_CMD_CHANNEL_SWITCH, MCU_Q_SET, NULL);
|
||||
ret = mt7603_mcu_msg_send(dev, skb, MCU_EXT_CMD_CHANNEL_SWITCH,
|
||||
MCU_Q_SET, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
+11
-9
@@ -39,7 +39,7 @@
|
||||
|
||||
#define MT7603_EEPROM_SIZE 1024
|
||||
|
||||
#define MT_AGG_SIZE_LIMIT(n) ((4 + 2 * (n & 1)) << (n / 2))
|
||||
#define MT_AGG_SIZE_LIMIT(n) ((4 + 2 * ((n) & 1)) << ((n) / 2))
|
||||
|
||||
#define MT7603_PRE_TBTT_TIME 5000 /* ms */
|
||||
|
||||
@@ -66,13 +66,14 @@ struct mt7603_sta {
|
||||
|
||||
struct mt7603_vif *vif;
|
||||
struct ieee80211_tx_rate rates[8];
|
||||
int rate_count;
|
||||
int n_rates;
|
||||
bool rate_probe;
|
||||
u8 rate_count;
|
||||
u8 n_rates;
|
||||
|
||||
int ampdu_count;
|
||||
int ampdu_tx_count;
|
||||
int ampdu_acked;
|
||||
u8 rate_probe;
|
||||
|
||||
u8 ampdu_count;
|
||||
u8 ampdu_tx_count;
|
||||
u8 ampdu_acked;
|
||||
};
|
||||
|
||||
struct mt7603_vif {
|
||||
@@ -114,7 +115,7 @@ struct mt7603_dev {
|
||||
|
||||
struct mt76_queue q_rx;
|
||||
|
||||
bool mcu_running;
|
||||
u8 mcu_running;
|
||||
|
||||
u8 beacon_mask;
|
||||
|
||||
@@ -198,7 +199,8 @@ int mt7603_mcu_set_channel(struct mt7603_dev *dev);
|
||||
int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);
|
||||
void mt7603_mcu_exit(struct mt7603_dev *dev);
|
||||
|
||||
void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, const u8 *mac_addr);
|
||||
void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
|
||||
const u8 *mac_addr);
|
||||
void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
|
||||
void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);
|
||||
void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
|
||||
|
||||
+1
-1
@@ -54,7 +54,7 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
|
||||
dev->mt76.rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
|
||||
(mt76_rr(dev, MT_HW_REV) & 0xff);
|
||||
dev_printk(KERN_INFO, dev->mt76.dev, "ASIC revision: %04x\n", dev->mt76.rev);
|
||||
dev_info(dev->mt76.dev, "ASIC revision: %04x\n", dev->mt76.rev);
|
||||
|
||||
ret = devm_request_irq(dev->mt76.dev, pdev->irq, mt7603_irq_handler,
|
||||
IRQF_SHARED, KBUILD_MODNAME, dev);
|
||||
|
||||
+17
-17
@@ -43,7 +43,7 @@
|
||||
#define MT_INT_RX_DONE(_n) BIT(_n)
|
||||
#define MT_INT_RX_DONE_ALL GENMASK(1, 0)
|
||||
#define MT_INT_TX_DONE_ALL GENMASK(19, 4)
|
||||
#define MT_INT_TX_DONE(_n) BIT(_n + 4)
|
||||
#define MT_INT_TX_DONE(_n) BIT((_n) + 4)
|
||||
|
||||
#define MT_INT_RX_COHERENT BIT(20)
|
||||
#define MT_INT_TX_COHERENT BIT(21)
|
||||
@@ -158,16 +158,16 @@
|
||||
#define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)
|
||||
#define MT_AGG_ARCR_SPE_DIS_TH GENMASK(27, 24)
|
||||
|
||||
|
||||
#define MT_AGG_ARUCR MT_WF_AGG(0x014)
|
||||
#define MT_AGG_ARDCR MT_WF_AGG(0x018)
|
||||
#define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * _n)
|
||||
#define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
|
||||
#define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n))
|
||||
#define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \
|
||||
MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
|
||||
MT_AGG_ARxCR_LIMIT_SHIFT(_n))
|
||||
|
||||
#define MT_AGG_LIMIT MT_WF_AGG(0x040)
|
||||
#define MT_AGG_LIMIT_1 MT_WF_AGG(0x044)
|
||||
#define MT_AGG_LIMIT_AC(n) GENMASK(((n) + 1) * 8 - 1, (n) * 8)
|
||||
#define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)
|
||||
|
||||
#define MT_AGG_BA_SIZE_LIMIT_0 MT_WF_AGG(0x048)
|
||||
#define MT_AGG_BA_SIZE_LIMIT_1 MT_WF_AGG(0x04c)
|
||||
@@ -244,7 +244,7 @@
|
||||
|
||||
#define MT_ARB_SCR MT_WF_ARB(0x080)
|
||||
#define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0)
|
||||
#define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n) (n * 2)
|
||||
#define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n) ((n) * 2)
|
||||
#define MT_ARB_SCR_TX_DISABLE BIT(8)
|
||||
#define MT_ARB_SCR_RX_DISABLE BIT(9)
|
||||
#define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28)
|
||||
@@ -321,7 +321,7 @@ enum {
|
||||
|
||||
#define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010)
|
||||
#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))
|
||||
#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)
|
||||
#define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16)
|
||||
#define MT_WMM_TXOP_MASK GENMASK(15, 0)
|
||||
|
||||
#define MT_TIMEOUT_CCK MT_WF_TMAC(0x090)
|
||||
@@ -376,12 +376,12 @@ enum {
|
||||
#define MT_WF_RFCR_DROP_NDPA BIT(20)
|
||||
#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
|
||||
|
||||
#define MT_BSSID0(idx) MT_WF_RMAC(0x004 + idx * 8)
|
||||
#define MT_BSSID1(idx) MT_WF_RMAC(0x008 + idx * 8)
|
||||
#define MT_BSSID0(idx) MT_WF_RMAC(0x004 + (idx) * 8)
|
||||
#define MT_BSSID1(idx) MT_WF_RMAC(0x008 + (idx) * 8)
|
||||
#define MT_BSSID1_VALID BIT(16)
|
||||
|
||||
#define MT_MAC_ADDR0(idx) MT_WF_RMAC(0x024 + idx * 8)
|
||||
#define MT_MAC_ADDR1(idx) MT_WF_RMAC(0x028 + idx * 8)
|
||||
#define MT_MAC_ADDR0(idx) MT_WF_RMAC(0x024 + (idx) * 8)
|
||||
#define MT_MAC_ADDR1(idx) MT_WF_RMAC(0x028 + (idx) * 8)
|
||||
#define MT_MAC_ADDR1_ADDR GENMASK(15, 0)
|
||||
#define MT_MAC_ADDR1_VALID BIT(16)
|
||||
|
||||
@@ -525,13 +525,16 @@ enum {
|
||||
#define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))
|
||||
#define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))
|
||||
#define MT_LED_STATUS_OFF_MASK GENMASK(31, 24)
|
||||
#define MT_LED_STATUS_OFF(_v) (((_v) << __ffs(MT_LED_STATUS_OFF_MASK)) & \
|
||||
#define MT_LED_STATUS_OFF(_v) (((_v) << \
|
||||
__ffs(MT_LED_STATUS_OFF_MASK)) & \
|
||||
MT_LED_STATUS_OFF_MASK)
|
||||
#define MT_LED_STATUS_ON_MASK GENMASK(23, 16)
|
||||
#define MT_LED_STATUS_ON(_v) (((_v) << __ffs(MT_LED_STATUS_ON_MASK)) & \
|
||||
#define MT_LED_STATUS_ON(_v) (((_v) << \
|
||||
__ffs(MT_LED_STATUS_ON_MASK)) & \
|
||||
MT_LED_STATUS_ON_MASK)
|
||||
#define MT_LED_STATUS_DURATION_MASK GENMASK(15, 0)
|
||||
#define MT_LED_STATUS_DURATION(_v) (((_v) << __ffs(MT_LED_STATUS_DURATION_MASK)) & \
|
||||
#define MT_LED_STATUS_DURATION(_v) (((_v) << \
|
||||
__ffs(MT_LED_STATUS_DURATION_MASK)) &\
|
||||
MT_LED_STATUS_DURATION_MASK)
|
||||
|
||||
#define MT_CLIENT_BASE_PHYS_ADDR 0x800c0000
|
||||
@@ -546,7 +549,6 @@ enum {
|
||||
#define MT_CLIENT_RESET_TX_R_E_1_S BIT(20)
|
||||
#define MT_CLIENT_RESET_TX_R_E_2_S BIT(21)
|
||||
|
||||
|
||||
#define MT_EFUSE_BASE 0x81070000
|
||||
|
||||
#define MT_EFUSE_BASE_CTRL 0x000
|
||||
@@ -634,7 +636,6 @@ enum {
|
||||
#define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17)
|
||||
#define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)
|
||||
|
||||
|
||||
#define MT_WTBL2_W0_PN_LO GENMASK(31, 0)
|
||||
|
||||
#define MT_WTBL2_W1_PN_HI GENMASK(15, 0)
|
||||
@@ -724,5 +725,4 @@ enum mt7603_cipher_type {
|
||||
MT_CIPHER_WAPI,
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
+1
-1
@@ -50,7 +50,7 @@ mt76_wmac_probe(struct platform_device *pdev)
|
||||
|
||||
dev->mt76.rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
|
||||
(mt76_rr(dev, MT_HW_REV) & 0xff);
|
||||
dev_printk(KERN_INFO, dev->mt76.dev, "ASIC revision: %04x\n", dev->mt76.rev);
|
||||
dev_info(dev->mt76.dev, "ASIC revision: %04x\n", dev->mt76.rev);
|
||||
|
||||
ret = devm_request_irq(dev->mt76.dev, irq, mt7603_irq_handler,
|
||||
IRQF_SHARED, KBUILD_MODNAME, dev);
|
||||
|
||||
Reference in New Issue
Block a user