mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 21:36:52 +00:00
Felix Fietkau
2fbd6baac1
If an interrupt is temporarily masked, its pending events need to be processed later, even if another interrupt happened in the mean time. Signed-off-by: Felix Fietkau <[email protected]>
274 lines
6.6 KiB
C
274 lines
6.6 KiB
C
#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include "mt7615.h"
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#include "regs.h"
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#include "mac.h"
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#include "../trace.h"
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const u32 mt7615e_reg_map[] = {
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[MT_TOP_CFG_BASE] = 0x01000,
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[MT_HW_BASE] = 0x01000,
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[MT_PCIE_REMAP_2] = 0x02504,
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[MT_ARB_BASE] = 0x20c00,
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[MT_HIF_BASE] = 0x04000,
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[MT_CSR_BASE] = 0x07000,
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[MT_PLE_BASE] = 0x08000,
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[MT_PSE_BASE] = 0x0c000,
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[MT_CFG_BASE] = 0x20200,
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[MT_AGG_BASE] = 0x20a00,
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[MT_TMAC_BASE] = 0x21000,
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[MT_RMAC_BASE] = 0x21200,
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[MT_DMA_BASE] = 0x21800,
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[MT_PF_BASE] = 0x22000,
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[MT_WTBL_BASE_ON] = 0x23000,
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[MT_WTBL_BASE_OFF] = 0x23400,
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[MT_LPON_BASE] = 0x24200,
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[MT_MIB_BASE] = 0x24800,
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[MT_WTBL_BASE_ADDR] = 0x30000,
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[MT_PCIE_REMAP_BASE2] = 0x80000,
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[MT_TOP_MISC_BASE] = 0xc0000,
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[MT_EFUSE_ADDR_BASE] = 0x81070000,
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};
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const u32 mt7663e_reg_map[] = {
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[MT_TOP_CFG_BASE] = 0x01000,
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[MT_HW_BASE] = 0x02000,
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[MT_DMA_SHDL_BASE] = 0x06000,
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[MT_PCIE_REMAP_2] = 0x0700c,
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[MT_ARB_BASE] = 0x20c00,
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[MT_HIF_BASE] = 0x04000,
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[MT_CSR_BASE] = 0x07000,
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[MT_PLE_BASE] = 0x08000,
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[MT_PSE_BASE] = 0x0c000,
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[MT_PP_BASE] = 0x0e000,
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[MT_CFG_BASE] = 0x20000,
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[MT_AGG_BASE] = 0x22000,
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[MT_TMAC_BASE] = 0x24000,
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[MT_RMAC_BASE] = 0x25000,
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[MT_DMA_BASE] = 0x27000,
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[MT_PF_BASE] = 0x28000,
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[MT_WTBL_BASE_ON] = 0x29000,
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[MT_WTBL_BASE_OFF] = 0x29800,
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[MT_LPON_BASE] = 0x2b000,
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[MT_MIB_BASE] = 0x2d000,
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[MT_WTBL_BASE_ADDR] = 0x30000,
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[MT_PCIE_REMAP_BASE2] = 0x90000,
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[MT_TOP_MISC_BASE] = 0xc0000,
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[MT_EFUSE_ADDR_BASE] = 0x78011000,
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};
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u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr)
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{
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u32 base, offset;
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if (is_mt7663(&dev->mt76)) {
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base = addr & MT7663_MCU_PCIE_REMAP_2_BASE;
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offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET;
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} else {
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base = addr & MT_MCU_PCIE_REMAP_2_BASE;
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offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
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}
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mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base);
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return MT_PCIE_REMAP_BASE_2 + offset;
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}
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static void
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mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
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{
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struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
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mt7615_irq_enable(dev, MT_INT_RX_DONE(q));
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}
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static irqreturn_t mt7615_irq_handler(int irq, void *dev_instance)
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{
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struct mt7615_dev *dev = dev_instance;
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mt76_wr(dev, MT_INT_MASK_CSR, 0);
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
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return IRQ_NONE;
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tasklet_schedule(&dev->irq_tasklet);
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return IRQ_HANDLED;
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}
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static void mt7615_irq_tasklet(unsigned long data)
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{
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struct mt7615_dev *dev = (struct mt7615_dev *)data;
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u32 intr, mask = 0;
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mt76_wr(dev, MT_INT_MASK_CSR, 0);
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intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
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intr &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
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trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
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mask |= intr & MT_INT_RX_DONE_ALL;
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if (intr & MT_INT_TX_DONE_ALL)
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mask |= MT_INT_TX_DONE_ALL;
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mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
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if (intr & MT_INT_TX_DONE_ALL)
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napi_schedule(&dev->mt76.tx_napi);
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if (intr & MT_INT_RX_DONE(0))
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napi_schedule(&dev->mt76.napi[0]);
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if (intr & MT_INT_RX_DONE(1))
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napi_schedule(&dev->mt76.napi[1]);
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if (intr & MT_INT_MCU_CMD) {
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u32 val = mt76_rr(dev, MT_MCU_CMD);
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if (val & MT_MCU_CMD_ERROR_MASK) {
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dev->reset_state = val;
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ieee80211_queue_work(mt76_hw(dev), &dev->reset_work);
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wake_up(&dev->reset_wait);
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}
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}
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}
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static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)
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{
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if (addr < 0x100000)
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return addr;
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return mt7615_reg_map(dev, addr);
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}
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static u32 mt7615_rr(struct mt76_dev *mdev, u32 offset)
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{
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struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
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u32 addr = __mt7615_reg_addr(dev, offset);
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return dev->bus_ops->rr(mdev, addr);
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}
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static void mt7615_wr(struct mt76_dev *mdev, u32 offset, u32 val)
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{
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struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
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u32 addr = __mt7615_reg_addr(dev, offset);
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dev->bus_ops->wr(mdev, addr, val);
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}
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static u32 mt7615_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
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{
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struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
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u32 addr = __mt7615_reg_addr(dev, offset);
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return dev->bus_ops->rmw(mdev, addr, mask, val);
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}
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int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
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int irq, const u32 *map)
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{
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static const struct mt76_driver_ops drv_ops = {
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/* txwi_size = txd size + txp size */
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.txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common),
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.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
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.survey_flags = SURVEY_INFO_TIME_TX |
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SURVEY_INFO_TIME_RX |
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SURVEY_INFO_TIME_BSS_RX,
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.tx_prepare_skb = mt7615_tx_prepare_skb,
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.tx_complete_skb = mt7615_tx_complete_skb,
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.rx_skb = mt7615_queue_rx_skb,
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.rx_poll_complete = mt7615_rx_poll_complete,
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.sta_ps = mt7615_sta_ps,
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.sta_add = mt7615_mac_sta_add,
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.sta_remove = mt7615_mac_sta_remove,
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.update_survey = mt7615_update_channel,
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};
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struct mt76_bus_ops *bus_ops;
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struct ieee80211_ops *ops;
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struct mt7615_dev *dev;
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struct mt76_dev *mdev;
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int ret;
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ops = devm_kmemdup(pdev, &mt7615_ops, sizeof(mt7615_ops), GFP_KERNEL);
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if (!ops)
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return -ENOMEM;
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mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops);
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if (!mdev)
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return -ENOMEM;
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dev = container_of(mdev, struct mt7615_dev, mt76);
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mt76_mmio_init(&dev->mt76, mem_base);
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tasklet_init(&dev->irq_tasklet, mt7615_irq_tasklet, (unsigned long)dev);
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dev->reg_map = map;
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dev->ops = ops;
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mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
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(mt76_rr(dev, MT_HW_REV) & 0xff);
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dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
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dev->bus_ops = dev->mt76.bus;
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bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
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GFP_KERNEL);
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if (!bus_ops) {
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ret = -ENOMEM;
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goto error;
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}
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bus_ops->rr = mt7615_rr;
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bus_ops->wr = mt7615_wr;
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bus_ops->rmw = mt7615_rmw;
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dev->mt76.bus = bus_ops;
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mt76_wr(dev, MT_INT_MASK_CSR, 0);
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ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler,
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IRQF_SHARED, KBUILD_MODNAME, dev);
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if (ret)
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goto error;
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if (is_mt7663(mdev))
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mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1);
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ret = mt7615_register_device(dev);
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if (ret)
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goto error;
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return 0;
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error:
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ieee80211_free_hw(mt76_hw(dev));
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return ret;
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}
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static int __init mt7615_init(void)
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{
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int ret;
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ret = pci_register_driver(&mt7615_pci_driver);
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_MT7622_WMAC)) {
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ret = platform_driver_register(&mt7622_wmac_driver);
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if (ret)
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pci_unregister_driver(&mt7615_pci_driver);
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}
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return ret;
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}
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static void __exit mt7615_exit(void)
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{
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if (IS_ENABLED(CONFIG_MT7622_WMAC))
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platform_driver_unregister(&mt7622_wmac_driver);
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pci_unregister_driver(&mt7615_pci_driver);
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}
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module_init(mt7615_init);
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module_exit(mt7615_exit);
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MODULE_LICENSE("Dual BSD/GPL");
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