mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 05:16:57 +00:00
Felix Fietkau
04017929f6
mt76_mmio_write_copy() and mt76_mmio_read_copy() iterate up to
ALIGN(len, 4), so a length that is not a multiple of four reads past the
source buffer (write_copy) or writes past the destination (read_copy).
Copy the aligned body in the loop and handle the remaining tail through a
4-byte bounce buffer, keeping the register access width unchanged.
Fixes: 2df00805f7db ("wifi: mt76: mmio_*_copy fix byte order and alignment")
Signed-off-by: Felix Fietkau <[email protected]>
129 lines
2.7 KiB
C
129 lines
2.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (C) 2016 Felix Fietkau <[email protected]>
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*/
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#include "mt76.h"
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#include "dma.h"
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#include "trace.h"
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static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset)
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{
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u32 val;
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val = readl(dev->mmio.regs + offset);
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trace_reg_rr(dev, offset, val);
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return val;
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}
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static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
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{
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trace_reg_wr(dev, offset, val);
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writel(val, dev->mmio.regs + offset);
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}
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static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
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{
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val |= mt76_mmio_rr(dev, offset) & ~mask;
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mt76_mmio_wr(dev, offset, val);
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return val;
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}
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static void mt76_mmio_write_copy(struct mt76_dev *dev, u32 offset,
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const void *data, int len)
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{
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int i;
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for (i = 0; i + 4 <= len; i += 4)
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writel(get_unaligned_le32(data + i),
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dev->mmio.regs + offset + i);
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if (i < len) {
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u8 tmp[4] = {};
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memcpy(tmp, data + i, len - i);
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writel(get_unaligned_le32(tmp), dev->mmio.regs + offset + i);
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}
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}
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static void mt76_mmio_read_copy(struct mt76_dev *dev, u32 offset,
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void *data, int len)
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{
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int i;
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for (i = 0; i + 4 <= len; i += 4)
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put_unaligned_le32(readl(dev->mmio.regs + offset + i),
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data + i);
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if (i < len) {
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u8 tmp[4];
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put_unaligned_le32(readl(dev->mmio.regs + offset + i), tmp);
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memcpy(data + i, tmp, len - i);
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}
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}
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static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base,
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const struct mt76_reg_pair *data, int len)
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{
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while (len > 0) {
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mt76_mmio_wr(dev, data->reg, data->value);
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data++;
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len--;
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}
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return 0;
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}
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static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base,
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struct mt76_reg_pair *data, int len)
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{
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while (len > 0) {
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data->value = mt76_mmio_rr(dev, data->reg);
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data++;
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len--;
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}
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return 0;
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}
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void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
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u32 clear, u32 set)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev->mmio.irq_lock, flags);
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dev->mmio.irqmask &= ~clear;
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dev->mmio.irqmask |= set;
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if (addr) {
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if (mtk_wed_device_active(&dev->mmio.wed))
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mtk_wed_device_irq_set_mask(&dev->mmio.wed,
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dev->mmio.irqmask);
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else
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mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
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}
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spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
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}
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EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
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void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
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{
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static const struct mt76_bus_ops mt76_mmio_ops = {
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.rr = mt76_mmio_rr,
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.rmw = mt76_mmio_rmw,
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.wr = mt76_mmio_wr,
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.write_copy = mt76_mmio_write_copy,
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.read_copy = mt76_mmio_read_copy,
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.wr_rp = mt76_mmio_wr_rp,
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.rd_rp = mt76_mmio_rd_rp,
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.type = MT76_BUS_MMIO,
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};
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dev->bus = &mt76_mmio_ops;
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dev->mmio.regs = regs;
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spin_lock_init(&dev->mmio.irq_lock);
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}
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EXPORT_SYMBOL_GPL(mt76_mmio_init);
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