mirror of
https://github.com/outbackdingo/mt76.git
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mt7603: use indirect rate table update
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
@@ -66,7 +66,7 @@ struct mt7603_mcu {
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struct mt7603_sta {
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struct mt76_wcid wcid; /* must be first */
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struct ieee80211_tx_rate rates[4];
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struct ieee80211_tx_rate rates[8];
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int n_rates;
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int pid;
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+32
-11
@@ -482,44 +482,65 @@ void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta)
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bool stbc = false;
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int n_rates = sta->n_rates;
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u8 bw, bw_prev, bw_idx = 0;
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u16 val[4];
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u16 val[8];
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u32 w9 = mt76_rr(dev, addr + 9 * 4);
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int i;
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mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
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if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
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return;
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for (i = n_rates; i < 4; i++)
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for (i = n_rates; i < 8; i++)
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rates[i] = rates[n_rates - 1];
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w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
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MT_WTBL2_W9_SHORT_GI_80;
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val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
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mt76_rmw_field(dev, addr + 9 * 4, MT_WTBL2_W9_BW_CAP, bw);
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mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE1, val[0]);
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w9 |= MT76_SET(MT_WTBL2_W9_CC_BW_SEL, bw);
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w9 |= MT76_SET(MT_WTBL2_W9_BW_CAP, bw);
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bw_prev = bw;
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val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
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mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE2, val[1]);
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if (bw_prev < bw && !bw_idx)
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bw_idx = 1;
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bw_prev = bw;
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val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
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mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE3_LO, val[2]);
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mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE3_HI, val[2] >> 4);
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if (bw_prev < bw && !bw_idx)
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bw_idx = 2;
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bw_prev = bw;
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val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
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mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE4, val[3]);
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if (bw_prev < bw && !bw_idx)
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bw_idx = 3;
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mt76_rmw_field(dev, addr + 9 * 4, MT_WTBL2_W9_CHANGE_BW_RATE,
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w9 |= MT76_SET(MT_WTBL2_W9_CHANGE_BW_RATE,
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bw_idx ? bw_idx - 1 : 7);
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mt76_wr(dev, MT_WTBL_RIUCR0, w9);
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mt76_wr(dev, MT_WTBL_RIUCR1,
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MT76_SET(MT_WTBL_RIUCR1_RATE0, val[0]) |
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MT76_SET(MT_WTBL_RIUCR1_RATE1, val[1]) |
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MT76_SET(MT_WTBL_RIUCR1_RATE2_LO, val[2]));
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mt76_wr(dev, MT_WTBL_RIUCR2,
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MT76_SET(MT_WTBL_RIUCR2_RATE2_HI, val[2] >> 8) |
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MT76_SET(MT_WTBL_RIUCR2_RATE3, val[3]) |
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MT76_SET(MT_WTBL_RIUCR2_RATE4, val[4]) |
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MT76_SET(MT_WTBL_RIUCR2_RATE5_LO, val[5]));
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mt76_wr(dev, MT_WTBL_RIUCR3,
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MT76_SET(MT_WTBL_RIUCR3_RATE5_HI, val[5] >> 4) |
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MT76_SET(MT_WTBL_RIUCR3_RATE6, val[6]) |
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MT76_SET(MT_WTBL_RIUCR3_RATE7, val[7]));
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mt76_wr(dev, MT_WTBL_UPDATE,
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MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
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MT_WTBL_UPDATE_WTBL2 |
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MT_WTBL_UPDATE_RATE_UPDATE |
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MT_WTBL_UPDATE_TX_COUNT_CLEAR);
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sta->wcid.tx_rate_set = true;
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}
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static enum mt7603_cipher_type
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@@ -481,7 +481,6 @@ mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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}
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msta->n_rates = i;
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mt7603_wtbl_set_rates(dev, msta);
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msta->wcid.tx_rate_set = true;
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}
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static void mt7603_set_coverage_class(struct ieee80211_hw *hw,
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