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mt7603: more mac init

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2015-12-07 02:35:12 +01:00
parent 8bfe790d48
commit bb8f947cc5
3 changed files with 35 additions and 10 deletions
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mt7603_dma.c
+2
View File
@@ -295,6 +295,8 @@ int mt7603_dma_init(struct mt7603_dev *dev)
mt7603_dma_rx_fill(dev, &dev->q_rx);
mt7603_dma_rx_fill(dev, &dev->mcu.q_rx);
mt76_wr(dev, MT_DELAY_INT_CFG, 0);
return 0;
}
mt7603_init.c
+24 -10
View File
@@ -29,30 +29,45 @@ struct mt7603_dev *mt7603_alloc_device(struct device *pdev)
return dev;
}
int mt7603_mac_reset(struct mt7603_dev *dev)
static bool
wait_for_wpdma(struct mt7603_dev *dev)
{
return mt76_poll(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
0, 1000);
}
static int
mt7603_mac_reset(struct mt7603_dev *dev)
{
u32 val;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
MT_WPDMA_GLO_CFG_RX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
mt76_wr(dev, MT_DMA_DCR0, 0x1000);
mt76_wr(dev, MT_DMA_DCR1, GENMASK(13, 11));
val = mt76_rr(dev, MT_DMA_VCFR0);
val &= ~BIT(0); /* To HIF */
val |= BIT(13); /* Rx Ring 1 */
mt76_wr(dev, MT_DMA_VCFR0, val);
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
return 0;
}
int mt7603_mac_start(struct mt7603_dev *dev)
{
wait_for_wpdma(dev);
udelay(50);
mt76_set(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_EN);
mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
return 0;
}
@@ -69,7 +84,6 @@ int mt7603_init_hardware(struct mt7603_dev *dev)
return ret;
set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
ret = mt7603_mac_start(dev);
if (ret)
mt7603_regs.h
+9
View File
@@ -34,6 +34,7 @@
#define MT_INT_SOURCE_CSR MT_HIF(0x200)
#define MT_INT_MASK_CSR MT_HIF(0x204)
#define MT_DELAY_INT_CFG MT_HIF(0x204)
#define MT_INT_RX_DONE(_n) BIT(_n)
#define MT_INT_RX_DONE_ALL GENMASK(1, 0)
@@ -71,6 +72,14 @@
#define MT_SCH_4_FORCE_QID GENMASK(4, 0)
#define MT_SCH_4_BYPASS BIT(5)
#define MT_WF_DMA_BASE 0x21c00
#define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))
#define MT_DMA_DCR0 MT_WF_DMA(0x000)
#define MT_DMA_DCR1 MT_WF_DMA(0x004)
#define MT_DMA_RCFR0 MT_WF_DMA(0x070)
#define MT_DMA_VCFR0 MT_WF_DMA(0x07c)
#define MT_PCIE_REMAP_BASE_1 0x40000
#define MT_PCIE_REMAP_BASE_2 0x80000