mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
core: fix checkpatch errors
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
@@ -64,7 +64,8 @@ struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
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return NULL;
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debugfs_create_u32("regidx", S_IRUSR | S_IWUSR, dir, &dev->debugfs_reg);
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debugfs_create_file("regval", S_IRUSR | S_IWUSR, dir, dev, &fops_regval);
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debugfs_create_file("regval", S_IRUSR | S_IWUSR, dir, dev,
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&fops_regval);
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debugfs_create_blob("eeprom", S_IRUSR, dir, &dev->eeprom);
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if (dev->otp.data)
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debugfs_create_blob("otp", S_IRUSR, dir, &dev->otp);
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@@ -82,10 +82,10 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
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desc = &q->desc[idx];
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ACCESS_ONCE(desc->buf0) = cpu_to_le32(buf0);
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ACCESS_ONCE(desc->buf1) = cpu_to_le32(buf1);
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ACCESS_ONCE(desc->info) = cpu_to_le32(info);
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ACCESS_ONCE(desc->ctrl) = cpu_to_le32(ctrl);
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WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
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WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
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WRITE_ONCE(desc->info, cpu_to_le32(info));
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WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
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q->queued++;
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}
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@@ -101,25 +101,27 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
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struct mt76_queue_entry *prev_e)
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{
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struct mt76_queue_entry *e = &q->entry[idx];
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__le32 __ctrl = ACCESS_ONCE(q->desc[idx].ctrl);
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__le32 __ctrl = READ_ONCE(q->desc[idx].ctrl);
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u32 ctrl = le32_to_cpu(__ctrl);
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if (!e->txwi || !e->skb) {
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__le32 addr = ACCESS_ONCE(q->desc[idx].buf0);
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__le32 addr = READ_ONCE(q->desc[idx].buf0);
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u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
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dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
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DMA_TO_DEVICE);
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}
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if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) {
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__le32 addr = ACCESS_ONCE(q->desc[idx].buf1);
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__le32 addr = READ_ONCE(q->desc[idx].buf1);
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u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl);
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dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
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DMA_TO_DEVICE);
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}
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if (e->txwi == DMA_DUMMY_TXWI)
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e->txwi = NULL;
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e->txwi = NULL;
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*prev_e = *e;
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memset(e, 0, sizeof(*e));
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@@ -128,7 +130,8 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
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static void
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mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
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{
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q->tail = q->head = ioread32(&q->regs->dma_idx);
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q->head = ioread32(&q->regs->dma_idx);
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q->tail = q->head;
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iowrite32(q->head, &q->regs->cpu_idx);
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}
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@@ -166,7 +169,7 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
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q->queued--;
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if (!flush && q->tail == last)
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last = ioread32(&q->regs->dma_idx);
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last = ioread32(&q->regs->dma_idx);
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}
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if (!flush)
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@@ -191,9 +194,9 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
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void *buf = e->buf;
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int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
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buf_addr = ACCESS_ONCE(desc->buf0);
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buf_addr = READ_ONCE(desc->buf0);
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if (len) {
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u32 ctl = ACCESS_ONCE(desc->ctrl);
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u32 ctl = READ_ONCE(desc->ctrl);
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*len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
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*more = !(ctl & MT_DMA_CTL_LAST_SEC0);
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}
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@@ -310,7 +313,7 @@ mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
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static void
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mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
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int len, bool more)
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int len, bool more)
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{
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struct page *page = virt_to_head_page(data);
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int offset = data - page_address(page);
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@@ -361,7 +364,7 @@ mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
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}
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if (q == &dev->q_rx[MT_RXQ_MCU]) {
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u32 * rxfce = (u32 *) skb->cb;
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u32 *rxfce = (u32 *) skb->cb;
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*rxfce = info;
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}
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@@ -407,7 +410,8 @@ mt76_dma_init(struct mt76_dev *dev)
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init_dummy_netdev(&dev->napi_dev);
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for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {
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netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll, 64);
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netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll,
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64);
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mt76_dma_rx_fill(dev, &dev->q_rx[i], false);
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skb_queue_head_init(&dev->rx_skb[i]);
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napi_enable(&dev->napi[i]);
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@@ -102,11 +102,10 @@ mt76_eeprom_override(struct mt76_dev *dev)
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if (!is_valid_ether_addr(dev->macaddr)) {
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eth_random_addr(dev->macaddr);
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dev_printk(KERN_INFO, dev->dev,
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"Invalid MAC address, using random address %pM\n",
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dev->macaddr);
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dev_info(dev->dev,
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"Invalid MAC address, using random address %pM\n",
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dev->macaddr);
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}
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}
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EXPORT_SYMBOL_GPL(mt76_eeprom_override);
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+5
-5
@@ -120,7 +120,7 @@ mt76_init_sband(struct mt76_dev *dev, struct mt76_sband *msband,
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ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
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if (!vht)
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return 0;
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return 0;
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vht_cap = &sband->vht_cap;
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vht_cap->vht_supported = true;
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@@ -137,9 +137,9 @@ mt76_init_sband(struct mt76_dev *dev, struct mt76_sband *msband,
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vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
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vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
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vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC |
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IEEE80211_VHT_CAP_TXSTBC |
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IEEE80211_VHT_CAP_RXSTBC_1 |
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IEEE80211_VHT_CAP_SHORT_GI_80;
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IEEE80211_VHT_CAP_TXSTBC |
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IEEE80211_VHT_CAP_RXSTBC_1 |
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IEEE80211_VHT_CAP_SHORT_GI_80;
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return 0;
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}
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@@ -267,7 +267,7 @@ void mt76_set_channel(struct mt76_dev *dev)
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EXPORT_SYMBOL_GPL(mt76_set_channel);
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int mt76_get_survey(struct ieee80211_hw *hw, int idx,
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struct survey_info *survey)
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struct survey_info *survey)
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{
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struct mt76_dev *dev = hw->priv;
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struct mt76_sband *sband;
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@@ -40,7 +40,8 @@ static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
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return val;
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}
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static void mt76_mmio_copy(struct mt76_dev *dev, u32 offset, const void *data, int len)
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static void mt76_mmio_copy(struct mt76_dev *dev, u32 offset, const void *data,
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int len)
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{
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__iowrite32_copy(dev->regs + offset, data, len >> 2);
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}
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@@ -35,7 +35,8 @@ struct mt76_bus_ops {
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u32 (*rr)(struct mt76_dev *dev, u32 offset);
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void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
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u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
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void (*copy)(struct mt76_dev *dev, u32 offset, const void *data, int len);
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void (*copy)(struct mt76_dev *dev, u32 offset, const void *data,
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int len);
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};
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enum mt76_txq_id {
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@@ -114,7 +115,8 @@ struct mt76_queue_ops {
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void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
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void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush);
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void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid,
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bool flush);
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void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
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};
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@@ -170,7 +172,7 @@ struct mt76_driver_ops {
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struct ieee80211_sta *sta, u32 *tx_info);
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void (*tx_complete_skb)(struct mt76_dev *dev, struct mt76_queue *q,
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struct mt76_queue_entry *e, bool flush);
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struct mt76_queue_entry *e, bool flush);
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void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
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struct sk_buff *skb);
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@@ -259,7 +261,7 @@ struct mt76_rate_power {
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#define mt76_hw(dev) (dev)->mt76.hw
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bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout);
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int timeout);
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#define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
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@@ -318,6 +320,7 @@ static inline struct ieee80211_txq *
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mtxq_to_txq(struct mt76_txq *mtxq)
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{
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void *ptr = mtxq;
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return container_of(ptr, struct ieee80211_txq, drv_priv);
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}
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@@ -342,7 +345,7 @@ void mt76_release_buffered_frames(struct ieee80211_hw *hw,
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bool more_data);
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void mt76_set_channel(struct mt76_dev *dev);
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int mt76_get_survey(struct ieee80211_hw *hw, int idx,
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struct survey_info *survey);
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struct survey_info *survey);
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/* internal */
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void mt76_tx_free(struct mt76_dev *dev);
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@@ -28,7 +28,8 @@ mt76_alloc_txwi(struct mt76_dev *dev)
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if (!t)
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return NULL;
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addr = dma_map_single(dev->dev, &t->txwi, sizeof(t->txwi), DMA_TO_DEVICE);
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addr = dma_map_single(dev->dev, &t->txwi, sizeof(t->txwi),
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DMA_TO_DEVICE);
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t->dma_addr = addr;
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return t;
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@@ -135,7 +136,8 @@ int mt76_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
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if (n == ARRAY_SIZE(buf))
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goto unmap;
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addr = dma_map_single(dev->dev, iter->data, iter->len, DMA_TO_DEVICE);
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addr = dma_map_single(dev->dev, iter->data, iter->len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev->dev, addr))
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goto unmap;
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@@ -151,7 +153,8 @@ int mt76_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
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unmap:
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ret = -ENOMEM;
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for (n--; n > 0; n--)
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dma_unmap_single(dev->dev, buf[n].addr, buf[n].len, DMA_TO_DEVICE);
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dma_unmap_single(dev->dev, buf[n].addr, buf[n].len,
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DMA_TO_DEVICE);
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free:
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e.skb = skb;
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@@ -454,7 +457,7 @@ void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta,
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spin_lock_bh(&mtxq->hwq->lock);
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mtxq->send_bar = mtxq->aggr && send_bar;
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if (!list_empty(&mtxq->list))
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list_del_init(&mtxq->list);
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list_del_init(&mtxq->list);
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spin_unlock_bh(&mtxq->hwq->lock);
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}
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}
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