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https://github.com/outbackdingo/mt76.git
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mt76: mt7915: only set int1 when using the second hif
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
+8
-5
@@ -103,11 +103,13 @@ static irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
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intr &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
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intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
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intr1 &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
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if (dev->hif2) {
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intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
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intr1 &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
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intr |= intr1;
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intr |= intr1;
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}
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
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return IRQ_NONE;
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@@ -162,6 +164,8 @@ static void mt7915_pci_init_hif2(struct mt7915_dev *dev)
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dev->hif2 = hif;
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mt76_wr(dev, MT_INT1_MASK_CSR, 0);
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if (devm_request_irq(dev->mt76.dev, hif->irq, mt7915_irq_handler,
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IRQF_SHARED, KBUILD_MODNAME "-hif", dev)) {
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mt7915_put_hif2(hif);
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@@ -245,7 +249,6 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
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dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
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mt76_wr(dev, MT_INT_MASK_CSR, 0);
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mt76_wr(dev, MT_INT1_MASK_CSR, 0);
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/* master switch of PCIe tnterrupt enable */
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mt7915_l1_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
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