gitops/mt76
1
0
Fork 0
mirror of https://github.com/outbackdingo/mt76.git synced 2026-10-24 13:26:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

move more dma processing code to mt76.ko

Browse Source 
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2015-12-06 22:54:47 +01:00
parent 73b49b6c15
commit 85e4dbfa00
3 changed files with 54 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files
dma.c
+26 -1
View File
@@ -89,6 +89,31 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
memset(e, 0, sizeof(*e));
}
static void
mt76_dma_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
void (*done)(struct mt76_dev *dev, struct mt76_queue *q,
struct mt76_queue_entry *e))
{
struct mt76_queue_entry entry;
int last;
if (flush)
last = -1;
else
last = ioread32(&q->regs->dma_idx);
while (q->queued && q->tail != last) {
mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
done(dev, q, &entry);
q->tail = (q->tail + 1) % q->ndesc;
q->queued--;
if (q->tail == last)
last = ioread32(&q->regs->dma_idx);
}
}
static int
mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
{
@@ -117,7 +142,7 @@ static const struct mt76_queue_ops mt76_dma_ops = {
.alloc = mt76_dma_alloc_queue,
.add_buf = mt76_dma_add_buf,
.dequeue = mt76_dma_dequeue,
.cleanup_idx = mt76_dma_tx_cleanup_idx,
.cleanup = mt76_dma_cleanup,
.kick = mt76_dma_kick_queue,
};
mt76.h
+8 -7
View File
@@ -73,8 +73,9 @@ struct mt76_queue_ops {
int (*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush);
void (*cleanup_idx)(struct mt76_dev *dev, struct mt76_queue *q, int idx,
struct mt76_queue_entry *e);
void (*cleanup)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
void (*done)(struct mt76_dev *dev, struct mt76_queue *q,
struct mt76_queue_entry *e));
void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
};
@@ -126,10 +127,10 @@ bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_add_buf(dev, ...) (dev)->mt76.queue_ops->add_buf(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_dequeue(dev, ...) (dev)->mt76.queue_ops->dequeue(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_cleanup_idx(dev, ...) (dev)->mt76.queue_ops->cleanup_idx(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_add_buf(dev, ...) (dev)->mt76.queue_ops->add_buf(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_dequeue(dev, ...) (dev)->mt76.queue_ops->dequeue(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_cleanup(dev, ...) (dev)->mt76.queue_ops->cleanup(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
#endif
mt76x2_dma.c
+20 -39
View File
@@ -214,49 +214,20 @@ free:
}
static void
mt76x2_tx_cleanup_entry(struct mt76x2_dev *dev, struct mt76_queue *q, int idx,
bool flush)
mt76x2_tx_cleanup_entry(struct mt76_dev *mdev, struct mt76_queue *q,
struct mt76_queue_entry *e)
{
struct mt76_queue_entry entry;
struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);
mt76_queue_cleanup_idx(dev, q, idx, &entry);
if (entry.txwi) {
mt76x2_mac_queue_txdone(dev, entry.skb, &entry.txwi->txwi);
mt76x2_put_txwi(dev, entry.txwi);
if (e->txwi) {
mt76x2_mac_queue_txdone(dev, e->skb, &e->txwi->txwi);
mt76x2_put_txwi(dev, e->txwi);
} else {
dev_kfree_skb_any(entry.skb);
dev_kfree_skb_any(e->skb);
}
if (entry.schedule) {
if (e->schedule)
q->swq_queued--;
if (!flush)
mt76x2_txq_schedule(dev, q);
}
}
static void
mt76x2_tx_cleanup_queue(struct mt76x2_dev *dev, struct mt76_queue *q, bool flush)
{
int last;
spin_lock_bh(&q->lock);
if (flush)
last = -1;
else
last = ioread32(&q->regs->dma_idx);
while (q->queued && q->tail != last) {
mt76x2_tx_cleanup_entry(dev, q, q->tail, flush);
q->tail = (q->tail + 1) % q->ndesc;
q->queued--;
if (q->tail == last)
last = ioread32(&q->regs->dma_idx);
}
spin_unlock_bh(&q->lock);
}
static void *
@@ -300,6 +271,16 @@ mt76x2_rx_cleanup(struct mt76x2_dev *dev, struct mt76_queue *q)
spin_unlock_bh(&q->lock);
}
static void
mt76_tx_cleanup(struct mt76x2_dev *dev, struct mt76_queue *q, bool flush)
{
spin_lock_bh(&q->lock);
mt76_queue_cleanup(dev, q, flush, mt76x2_tx_cleanup_entry);
if (!flush)
mt76x2_txq_schedule(dev, q);
spin_unlock_bh(&q->lock);
}
static int
mt76x2_init_tx_queue(struct mt76x2_dev *dev, struct mt76_queue *q,
int idx, int n_desc, bool mcu)
@@ -412,7 +393,7 @@ mt76x2_tx_tasklet(unsigned long data)
mt76x2_mac_process_tx_status_fifo(dev);
for (i = ARRAY_SIZE(dev->q_tx) - 1; i >= 0; i--)
mt76x2_tx_cleanup_queue(dev, &dev->q_tx[i], false);
mt76_tx_cleanup(dev, &dev->q_tx[i], false);
mt76x2_mac_poll_tx_status(dev, false);
mt76x2_irq_enable(dev, MT_INT_TX_DONE_ALL);
@@ -516,7 +497,7 @@ void mt76x2_dma_cleanup(struct mt76x2_dev *dev)
tasklet_kill(&dev->tx_tasklet);
tasklet_kill(&dev->rx_tasklet);
for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
mt76x2_tx_cleanup_queue(dev, &dev->q_tx[i], true);
mt76_tx_cleanup(dev, &dev->q_tx[i], true);
mt76x2_rx_cleanup(dev, &dev->q_rx);
mt76x2_rx_cleanup(dev, &dev->mcu.q_rx);