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move more register accessor functions to mt76.h

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2015-12-06 18:01:45 +01:00
parent 43c65c6de1
commit 62ecfb9730
7 changed files with 62 additions and 69 deletions
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mt76.h
+9
View File
@@ -40,6 +40,15 @@ struct mt76_dev {
#define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
#define mt76_wr_copy(dev, ...) (dev)->mt76.bus->copy(&((dev)->mt76), __VA_ARGS__)
#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
#define mt76_get_field(_dev, _reg, _field) \
MT76_GET(_field, mt76_rr(dev, _reg))
#define mt76_rmw_field(_dev, _reg, _field, _val) \
mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
#define mt76_hw(dev) (dev)->mt76.hw
void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
mt76x2.h
-16
View File
@@ -271,22 +271,6 @@ bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
void mt76_write_reg_pairs(struct mt76x2_dev *dev,
const struct mt76x2_reg_pair *data, int len);
#define mt76x2_get_field(_dev, _reg, _field) \
MT76_GET(_field, mt76_rr(dev, _reg))
#define mt76_rmw_field(_dev, _reg, _field, _val) \
mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
static inline u32 mt76x2_set(struct mt76x2_dev *dev, u32 offset, u32 val)
{
return mt76_rmw(dev, offset, 0, val);
}
static inline u32 mt76x2_clear(struct mt76x2_dev *dev, u32 offset, u32 val)
{
return mt76_rmw(dev, offset, val, 0);
}
static inline bool is_mt7612(struct mt76x2_dev *dev)
{
return (dev->rev >> 16) == 0x7612;
mt76x2_init.c
+34 -34
View File
@@ -55,8 +55,8 @@ mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
MT_PBF_SYS_CTRL_PBF_RESET |
MT_PBF_SYS_CTRL_ASY_RESET;
mt76x2_set(dev, MT_PBF_SYS_CTRL, val);
mt76x2_clear(dev, MT_PBF_SYS_CTRL, val);
mt76_set(dev, MT_PBF_SYS_CTRL, val);
mt76_clear(dev, MT_PBF_SYS_CTRL, val);
mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
@@ -150,7 +150,7 @@ mt76x2_fixup_xtal(struct mt76x2_dev *dev)
eep_val &= 0x7f;
mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
mt76x2_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
switch (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
@@ -206,15 +206,15 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
mt76_write_mac_initvals(dev);
mt76x2_fixup_xtal(dev);
mt76x2_clear(dev, MT_MAC_SYS_CTRL,
mt76_clear(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_RESET_CSR |
MT_MAC_SYS_CTRL_RESET_BBP);
if (is_mt7612(dev))
mt76x2_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
mt76x2_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
mt76x2_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
@@ -222,7 +222,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
mt76x2_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
@@ -256,7 +256,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
for (i = 0; i < 16; i++)
mt76_rr(dev, MT_TX_STAT_FIFO);
mt76x2_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76x2_init_beacon_offsets(dev);
mt76x2_set_tx_ackto(dev);
@@ -280,11 +280,11 @@ int mt76x2_mac_start(struct mt76x2_dev *dev)
wait_for_wpdma(dev);
udelay(50);
mt76x2_set(dev, MT_WPDMA_GLO_CFG,
mt76_set(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_EN);
mt76x2_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
@@ -322,11 +322,11 @@ void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
}
if (force && !stopped) {
mt76x2_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76x2_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76x2_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76x2_clear(dev, MT_BBP(CORE, 4), BIT(0));
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
}
mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
@@ -343,22 +343,22 @@ void mt76x2_mac_resume(struct mt76x2_dev *dev)
static void
mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
{
mt76x2_set(dev, 0x10130, BIT(0) | BIT(16));
mt76_set(dev, 0x10130, BIT(0) | BIT(16));
udelay(1);
mt76x2_clear(dev, 0x1001c, 0xff);
mt76x2_set(dev, 0x1001c, 0x30);
mt76_clear(dev, 0x1001c, 0xff);
mt76_set(dev, 0x1001c, 0x30);
mt76_wr(dev, 0x10014, 0x484f);
udelay(1);
mt76x2_set(dev, 0x10130, BIT(17));
mt76_set(dev, 0x10130, BIT(17));
udelay(125);
mt76x2_clear(dev, 0x10130, BIT(16));
mt76_clear(dev, 0x10130, BIT(16));
udelay(50);
mt76x2_set(dev, 0x1014c, BIT(19) | BIT(20));
mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
}
static void
@@ -367,20 +367,20 @@ mt76x2_power_on_rf(struct mt76x2_dev *dev, int unit)
int shift = unit ? 8 : 0;
/* Enable RF BG */
mt76x2_set(dev, 0x10130, BIT(0) << shift);
mt76_set(dev, 0x10130, BIT(0) << shift);
udelay(10);
/* Enable RFDIG LDO/AFE/ABB/ADDA */
mt76x2_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
udelay(10);
/* Switch RFDIG power to internal LDO */
mt76x2_clear(dev, 0x10130, BIT(2) << shift);
mt76_clear(dev, 0x10130, BIT(2) << shift);
udelay(10);
mt76x2_power_on_rf_patch(dev);
mt76x2_set(dev, 0x530, 0xf);
mt76_set(dev, 0x530, 0xf);
}
static void
@@ -389,7 +389,7 @@ mt76x2_power_on(struct mt76x2_dev *dev)
u32 val;
/* Turn on WL MTCMOS */
mt76x2_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
val = MT_WLAN_MTC_CTRL_STATE_UP |
MT_WLAN_MTC_CTRL_PWR_ACK |
@@ -397,23 +397,23 @@ mt76x2_power_on(struct mt76x2_dev *dev)
mt76x2_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
udelay(10);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
udelay(10);
mt76x2_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
/* Turn on AD/DA power down */
mt76x2_clear(dev, 0x11204, BIT(3));
mt76_clear(dev, 0x11204, BIT(3));
/* WLAN function enable */
mt76x2_set(dev, 0x10080, BIT(0));
mt76_set(dev, 0x10080, BIT(0));
/* Release BBP software reset */
mt76x2_clear(dev, 0x10064, BIT(18));
mt76_clear(dev, 0x10064, BIT(18));
mt76x2_power_on_rf(dev, 0);
mt76x2_power_on_rf(dev, 1);
@@ -425,7 +425,7 @@ void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
slottime += 3 * dev->coverage_class;
sifs = mt76x2_get_field(dev, MT_XIFS_TIME_CFG,
sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
MT_XIFS_TIME_CFG_OFDM_SIFS);
ackto = slottime + sifs;
mt76x2_mac.c
+1 -1
View File
@@ -603,7 +603,7 @@ __mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 bcn_idx, struct sk_buff *skb)
int i;
/* Prevent corrupt transmissions during update */
mt76x2_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
if (skb) {
ret = mt76_write_beacon(dev, beacon_addr, skb);
mt76x2_main.c
+6 -6
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@@ -232,7 +232,7 @@ mt76x2_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
msta->wcid.idx = idx;
msta->wcid.hw_key_idx = -1;
mt76x2_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
mt76x2_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76x2_txq_init(dev, sta->txq[i]);
@@ -257,7 +257,7 @@ mt76x2_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
rcu_assign_pointer(dev->wcid[idx], NULL);
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76x2_txq_remove(dev, sta->txq[i]);
mt76x2_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG);
mt76x2_mac_wcid_setup(dev, idx, 0, NULL);
mutex_unlock(&dev->mutex);
@@ -276,11 +276,11 @@ mt76x2_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
switch (cmd) {
case STA_NOTIFY_SLEEP:
msta->sleeping = true;
mt76x2_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76x2_stop_tx_queues(dev, sta);
break;
case STA_NOTIFY_AWAKE:
mt76x2_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
msta->sleeping = false;
break;
}
@@ -412,10 +412,10 @@ mt76x2_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
switch (action) {
case IEEE80211_AMPDU_RX_START:
mt76x2_set(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
break;
case IEEE80211_AMPDU_RX_STOP:
mt76x2_clear(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
break;
case IEEE80211_AMPDU_TX_OPERATIONAL:
mtxq->aggr = true;
mt76x2_mcu.c
+2 -2
View File
@@ -228,7 +228,7 @@ mt76pci_load_firmware(struct mt76x2_dev *dev)
val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
if (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
mt76x2_set(dev, MT_MCU_COM_REG0, BIT(30));
mt76_set(dev, MT_MCU_COM_REG0, BIT(30));
/* trigger firmware */
mt76_wr(dev, MT_MCU_INT_LEVEL, 2);
@@ -362,7 +362,7 @@ int mt76x2_mcu_calibrate(struct mt76x2_dev *dev, enum mcu_calibration type,
};
int ret;
mt76x2_clear(dev, MT_MCU_COM_REG0, BIT(31));
mt76_clear(dev, MT_MCU_COM_REG0, BIT(31));
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
ret = mt76x2_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP);
mt76x2_phy.c
+10 -10
View File
@@ -382,12 +382,12 @@ mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper)
{
switch (band) {
case IEEE80211_BAND_2GHZ:
mt76x2_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76x2_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
break;
case IEEE80211_BAND_5GHZ:
mt76x2_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76x2_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
break;
}
@@ -413,16 +413,16 @@ static void
mt76x2_set_tx_dac(struct mt76x2_dev *dev)
{
if (dev->chainmask & BIT(1))
mt76x2_set(dev, MT_BBP(TXBE, 5), 3);
mt76_set(dev, MT_BBP(TXBE, 5), 3);
else
mt76x2_clear(dev, MT_BBP(TXBE, 5), 3);
mt76_clear(dev, MT_BBP(TXBE, 5), 3);
}
static void
mt76x2_get_agc_gain(struct mt76x2_dev *dev, u8 *dest)
{
dest[0] = mt76x2_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
dest[1] = mt76x2_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
dest[0] = mt76_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
dest[1] = mt76_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
}
static int
@@ -588,7 +588,7 @@ int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
/* Enable LDPC Rx */
if (mt76xx_rev(dev) >= MT76XX_REV_E3)
mt76x2_set(dev, MT_BBP(RXO, 13), BIT(10));
mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
if (!dev->cal.init_cal_done) {
u8 val = mt76x2_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
@@ -674,7 +674,7 @@ mt76x2_phy_temp_compensate(struct mt76x2_dev *dev)
if (mt76x2_get_temp_comp(dev, &t))
return;
temp = mt76x2_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
temp -= t.temp_25_ref;
temp = (temp * 1789) / 1000 + 25;
dev->cal.temp = temp;