mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
mt7603: add another tx/rx watchdog check
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
@@ -33,7 +33,7 @@
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#define MT7603_PRE_TBTT_TIME 5000 /* ms */
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#define MT7603_WATCHDOG_TIME 1000 /* ms */
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#define MT7603_WATCHDOG_TIME 100 /* ms */
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#define MT7603_WATCHDOG_TIMEOUT 10 /* number of checks */
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enum {
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@@ -124,7 +124,10 @@ struct mt7603_dev {
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u8 beacon_mask;
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u8 tx_check;
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u8 rx_check;
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u8 txrx_check;
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u16 tx_dma_idx[4];
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u16 rx_dma_idx;
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struct delayed_work mac_work;
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struct tasklet_struct tx_tasklet;
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+56
-8
@@ -994,9 +994,6 @@ static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
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napi_disable(&dev->mt76.napi[0]);
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napi_disable(&dev->mt76.napi[1]);
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dev->tx_check = 0;
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dev->rx_check = 0;
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mt7603_beacon_set_timer(dev, -1, 0);
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mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
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@@ -1032,6 +1029,42 @@ static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
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return (val & BIT(8)) && (val & 0xf) != 0xf;
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}
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static bool mt7603_tx_rx_dma_busy(struct mt7603_dev *dev)
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{
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struct mt76_queue *q;
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u32 dma_idx, prev_dma_idx, val;
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int i;
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for (i = 0; i < 4; i++) {
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q = &dev->mt76.q_tx[i];
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prev_dma_idx = dev->tx_dma_idx[i];
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dev->tx_dma_idx[i] = dma_idx = ioread32(&q->regs->dma_idx);
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if (dma_idx != prev_dma_idx ||
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dma_idx == ioread32(&q->regs->cpu_idx))
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continue;
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val = mt76_rr(dev, MT_FC_RSV_COUNT_0);
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if (MT76_GET(MT_FC_RSV_COUNT_0_P0, val) > 0xa0)
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break;
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}
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if (i == 4)
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return false;
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q = &dev->mt76.q_rx[0];
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prev_dma_idx = dev->rx_dma_idx;
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dev->rx_dma_idx = dma_idx = ioread32(&q->regs->dma_idx);
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if (dma_idx != prev_dma_idx)
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return false;
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if (dma_idx == ioread32(&q->regs->cpu_idx))
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return false;
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val = mt76_rr(dev, MT_FC_SP2_Q0Q1);
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return MT76_GET(MT_FC_SP2_Q0Q1_SRC_COUNT_Q0, val) > 0x20;
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}
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void mt7603_mac_work(struct work_struct *work)
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{
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struct mt7603_dev *dev = container_of(work, struct mt7603_dev, mac_work.work);
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@@ -1041,18 +1074,33 @@ void mt7603_mac_work(struct work_struct *work)
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if (mt7603_tx_dma_busy(dev) ||
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dev->tx_check >= MT7603_WATCHDOG_TIMEOUT) {
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time = MT7603_WATCHDOG_TIME / 10;
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if (WARN_ON_ONCE(++dev->tx_check >= MT7603_WATCHDOG_TIMEOUT)) {
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mt7603_mac_watchdog_reset(dev);
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goto out;
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}
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if (WARN_ON_ONCE(++dev->tx_check >= MT7603_WATCHDOG_TIMEOUT))
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goto reset;
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} else {
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dev->tx_check = 0;
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}
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if (mt7603_tx_rx_dma_busy(dev) ||
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dev->txrx_check >= MT7603_WATCHDOG_TIMEOUT) {
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if (WARN_ON_ONCE(++dev->txrx_check >= MT7603_WATCHDOG_TIMEOUT))
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goto reset;
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} else {
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dev->txrx_check = 0;
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}
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out:
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ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work,
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msecs_to_jiffies(time));
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mutex_unlock(&dev->mutex);
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return;
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reset:
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dev->tx_check = 0;
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dev->txrx_check = 0;
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dev->rx_dma_idx = ~0;
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memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
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mt7603_mac_watchdog_reset(dev);
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goto out;
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}
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@@ -115,6 +115,14 @@
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#define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9)
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#define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12)
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#define MT_FC_RSV_COUNT_0 MT_PSE(0x13c)
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#define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0)
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#define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)
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#define MT_FC_SP2_Q0Q1 MT_PSE(0x14c)
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#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0)
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#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)
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#define MT_WF_PHY_BASE 0x10000
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#define MT_WF_PHY_OFFSET 0x1000
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#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
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