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mt76: mt7921: fix stats register definitions
Fix register definitions for mac80211 stats reporting.
Move mib counter reset to mt7921_get_stats routine.
Fixes: 163f4d22c118d ("mt76: mt7921: add MAC support")
Signed-off-by: Lorenzo Bianconi <[email protected]>
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
committed by
Felix Fietkau
parent
10a95da23c
commit
2856dc8fb5
+10
-21
@@ -1318,31 +1318,20 @@ mt7921_mac_update_mib_stats(struct mt7921_phy *phy)
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struct mib_stats *mib = &phy->mib;
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int i, aggr0 = 0, aggr1;
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memset(mib, 0, sizeof(*mib));
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mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(0),
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MT_MIB_SDR3_FCS_ERR_MASK);
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mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
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MT_MIB_SDR3_FCS_ERR_MASK);
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mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0),
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MT_MIB_ACK_FAIL_COUNT_MASK);
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mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0),
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MT_MIB_BA_FAIL_COUNT_MASK);
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mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0),
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MT_MIB_RTS_COUNT_MASK);
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mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0),
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MT_MIB_RTS_FAIL_COUNT_MASK);
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for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
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u32 val, val2;
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val = mt76_rr(dev, MT_MIB_MB_SDR1(0, i));
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val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
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if (val2 > mib->ack_fail_cnt)
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mib->ack_fail_cnt = val2;
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val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
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if (val2 > mib->ba_miss_cnt)
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mib->ba_miss_cnt = val2;
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val = mt76_rr(dev, MT_MIB_MB_SDR0(0, i));
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val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
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if (val2 > mib->rts_retries_cnt) {
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mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
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mib->rts_retries_cnt = val2;
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}
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val = mt76_rr(dev, MT_TX_AGG_CNT(0, i));
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val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
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@@ -831,11 +831,17 @@ mt7921_get_stats(struct ieee80211_hw *hw,
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struct mt7921_phy *phy = mt7921_hw_phy(hw);
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struct mib_stats *mib = &phy->mib;
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mt7921_mutex_acquire(phy->dev);
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stats->dot11RTSSuccessCount = mib->rts_cnt;
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stats->dot11RTSFailureCount = mib->rts_retries_cnt;
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stats->dot11FCSErrorCount = mib->fcs_err_cnt;
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stats->dot11ACKFailureCount = mib->ack_fail_cnt;
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memset(mib, 0, sizeof(*mib));
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mt7921_mutex_release(phy->dev);
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return 0;
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}
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+5
-5
@@ -102,11 +102,11 @@ struct mt7921_vif {
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};
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struct mib_stats {
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u16 ack_fail_cnt;
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u16 fcs_err_cnt;
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u16 rts_cnt;
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u16 rts_retries_cnt;
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u16 ba_miss_cnt;
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u32 ack_fail_cnt;
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u32 fcs_err_cnt;
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u32 rts_cnt;
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u32 rts_retries_cnt;
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u32 ba_miss_cnt;
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};
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struct mt7921_phy {
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+10
-5
@@ -96,8 +96,8 @@
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#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
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#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
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#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
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#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
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#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698)
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#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(31, 16)
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#define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
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#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
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@@ -121,9 +121,14 @@
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#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
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#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
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#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
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#define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688)
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#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690)
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#define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518)
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#define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520)
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#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
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#define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
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