mt76: add coverage class support

Add coverage class support to configure ACK timeout

Signed-off-by: Lorenzo Bianconi <[email protected]>
This commit is contained in:
Lorenzo Bianconi
2015-08-05 18:12:04 +02:00
committed by Felix Fietkau
parent 714f88015d
commit 17c5b83ee7
4 changed files with 37 additions and 0 deletions
+18
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@@ -259,6 +259,8 @@ int mt76_mac_reset(struct mt76_dev *dev, bool hard)
mt76_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76_init_beacon_offsets(dev);
mt76_set_tx_ackto(dev);
return 0;
}
@@ -417,6 +419,20 @@ mt76_power_on(struct mt76_dev *dev)
mt76_power_on_rf(dev, 1);
}
void mt76_set_tx_ackto(struct mt76_dev *dev)
{
u8 ackto, sifs, slottime = dev->slottime;
slottime += 3 * dev->coverage_class;
sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
MT_XIFS_TIME_CFG_OFDM_SIFS);
ackto = slottime + sifs;
mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
MT_TX_TIMEOUT_CFG_ACKTO, ackto);
}
static void
mt76_set_wlan_state(struct mt76_dev *dev, bool enable)
{
@@ -488,6 +504,8 @@ int mt76_init_hardware(struct mt76_dev *dev)
dev->chainmask = 0x202;
dev->slottime = 9;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
MT_WPDMA_GLO_CFG_BIG_ENDIAN |
+13
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@@ -180,6 +180,7 @@ mt76_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
if (changed & BSS_CHANGED_ERP_SLOT) {
int slottime = info->use_short_slot ? 9 : 20;
dev->slottime = slottime;
mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
}
@@ -447,6 +448,17 @@ mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76_mac_wcid_set_rate(dev, &msta->wcid, &rate);
}
static void mt76_set_coverage_class(struct ieee80211_hw *hw,
s16 coverage_class)
{
struct mt76_dev *dev = hw->priv;
mutex_lock(&dev->mutex);
dev->coverage_class = coverage_class;
mt76_set_tx_ackto(dev);
mutex_unlock(&dev->mutex);
}
const struct ieee80211_ops mt76_ops = {
.tx = mt76_tx,
.start = mt76_start,
@@ -469,6 +481,7 @@ const struct ieee80211_ops mt76_ops = {
.wake_tx_queue = mt76_wake_tx_queue,
.sta_rate_tbl_update = mt76_sta_rate_tbl_update,
.release_buffered_frames = mt76_release_buffered_frames,
.set_coverage_class = mt76_set_coverage_class,
};
void mt76_rx(struct mt76_dev *dev, struct sk_buff *skb)
+4
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@@ -232,6 +232,9 @@ struct mt76_dev {
s8 target_power;
s8 target_power_delta[2];
struct mt76_rate_power rate_power;
u8 coverage_class;
u8 slottime;
};
struct mt76_vif {
@@ -332,6 +335,7 @@ int mt76_init_hardware(struct mt76_dev *dev);
void mt76_stop_hardware(struct mt76_dev *dev);
int mt76_eeprom_init(struct mt76_dev *dev);
int mt76_apply_calibration_data(struct mt76_dev *dev, int channel);
void mt76_set_tx_ackto(struct mt76_dev *dev);
int mt76_phy_start(struct mt76_dev *dev);
int mt76_set_channel(struct mt76_dev *dev, struct cfg80211_chan_def *chandef);
+2
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@@ -333,6 +333,8 @@
#define MT_TX_RTS_FALLBACK BIT(24)
#define MT_TX_TIMEOUT_CFG 0x1348
#define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)
#define MT_TX_RETRY_CFG 0x134c
#define MT_VHT_HT_FBK_CFG1 0x1358