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phy: adjust per-rate tx powers according to power limits

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2015-07-28 15:01:51 +02:00
parent 902757f059
commit 0336b5d62a
4 changed files with 95 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
debugfs.c
+31
View File
@@ -65,6 +65,36 @@ mt76_ampdu_stat_open(struct inode *inode, struct file *f)
return single_open(f, mt76_ampdu_stat_read, inode->i_private);
}
static void
seq_puts_array(struct seq_file *file, const char *str, s8 *val, int len)
{
int i;
seq_printf(file, "%10s:", str);
for (i = 0; i < len; i++)
seq_printf(file, " %2d", val[i]);
seq_puts(file, "\n");
}
static int read_txpower(struct seq_file *file, void *data)
{
struct mt76_dev *dev = dev_get_drvdata(file->private);
seq_printf(file, "Target power: %d\n", dev->target_power);
seq_puts_array(file, "Delta", dev->target_power_delta,
ARRAY_SIZE(dev->target_power_delta));
seq_puts_array(file, "CCK", dev->rate_power.cck,
ARRAY_SIZE(dev->rate_power.cck));
seq_puts_array(file, "OFDM", dev->rate_power.ofdm,
ARRAY_SIZE(dev->rate_power.ofdm));
seq_puts_array(file, "HT", dev->rate_power.ht,
ARRAY_SIZE(dev->rate_power.ht));
seq_puts_array(file, "VHT", dev->rate_power.vht,
ARRAY_SIZE(dev->rate_power.vht));
return 0;
}
static const struct file_operations fops_ampdu_stat = {
.open = mt76_ampdu_stat_open,
.read = seq_read,
@@ -86,4 +116,5 @@ void mt76_init_debugfs(struct mt76_dev *dev)
debugfs_create_u32("regidx", S_IRUSR | S_IWUSR, dir, &dev->debugfs_reg);
debugfs_create_file("regval", S_IRUSR | S_IWUSR, dir, dev, &fops_regval);
debugfs_create_file("ampdu_stat", S_IRUSR, dir, dev, &fops_ampdu_stat);
debugfs_create_devm_seqfile(dev->dev, "txpower", dir, read_txpower);
}
eeprom.h
-12
View File
@@ -106,18 +106,6 @@ enum mt76_cal_channel_group {
__MT_CH_MAX
};
struct mt76_rate_power {
union {
struct {
s8 cck[4];
s8 ofdm[8];
s8 ht[16];
s8 vht[10];
};
s8 all[38];
};
};
struct mt76_tx_power_info {
u8 target_power;
mt76.h
+16
View File
@@ -141,6 +141,18 @@ struct mt76_hw_cap {
bool has_5ghz;
};
struct mt76_rate_power {
union {
struct {
s8 cck[4];
s8 ofdm[8];
s8 ht[16];
s8 vht[10];
};
s8 all[38];
};
};
struct mt76_dma_ops {
int (*queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
struct sk_buff *skb, struct mt76_wcid *wcid,
@@ -216,6 +228,10 @@ struct mt76_dev {
struct mt76_hw_cap cap;
u32 debugfs_reg;
s8 target_power;
s8 target_power_delta[2];
struct mt76_rate_power rate_power;
};
struct mt76_vif {
phy.c
+48 -25
View File
@@ -97,30 +97,6 @@ mt76_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
return val;
}
static void mt76_apply_rate_power_table(struct mt76_dev *dev)
{
struct mt76_rate_power t;
mt76_get_rate_power(dev, &t);
mt76_wr(dev, MT_TX_PWR_CFG_0,
mt76_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
mt76_wr(dev, MT_TX_PWR_CFG_1,
mt76_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[4]));
mt76_wr(dev, MT_TX_PWR_CFG_2,
mt76_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
mt76_wr(dev, MT_TX_PWR_CFG_3,
mt76_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
mt76_wr(dev, MT_TX_PWR_CFG_4,
mt76_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
mt76_wr(dev, MT_TX_PWR_CFG_7,
mt76_tx_power_mask(t.ofdm[4], t.vht[8], t.ht[6], t.vht[8]));
mt76_wr(dev, MT_TX_PWR_CFG_8,
mt76_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
mt76_wr(dev, MT_TX_PWR_CFG_9,
mt76_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
}
int mt76_phy_get_rssi(struct mt76_dev *dev, s8 rssi, int chain)
{
struct mt76_rx_freq_cal *cal = &dev->cal.rx;
@@ -141,11 +117,31 @@ mt76_txpower_check(int value)
return value;
}
static void
mt76_add_rate_power_offset(struct mt76_rate_power *r, int offset)
{
int i;
for (i = 0; i < sizeof(r->all); i++)
r->all[i] += offset;
}
static void
mt76_limit_rate_power(struct mt76_rate_power *r, int limit)
{
int i;
for (i = 0; i < sizeof(r->all); i++)
if (r->all[i] > limit)
r->all[i] = limit;
}
void mt76_phy_set_txpower(struct mt76_dev *dev)
{
enum nl80211_chan_width width = dev->chandef.width;
struct mt76_tx_power_info txp;
int txp_0, txp_1, delta = 0;
struct mt76_rate_power t;
mt76_get_power_info(dev, &txp);
@@ -161,6 +157,17 @@ void mt76_phy_set_txpower(struct mt76_dev *dev)
dev->txpower_cur = txp.target_power;
}
mt76_get_rate_power(dev, &t);
mt76_add_rate_power_offset(&t, txp.chain[0].target_power +
txp.chain[0].delta);
mt76_limit_rate_power(&t, dev->txpower_conf);
mt76_add_rate_power_offset(&t, -(txp.chain[0].target_power +
txp.chain[0].delta + delta));
dev->target_power = txp.chain[0].target_power;
dev->target_power_delta[0] = txp.chain[0].delta + delta;
dev->target_power_delta[1] = txp.chain[1].delta + delta;
dev->rate_power = t;
txp_0 = mt76_txpower_check(txp.chain[0].target_power +
txp.chain[0].delta + delta);
@@ -169,6 +176,23 @@ void mt76_phy_set_txpower(struct mt76_dev *dev)
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
mt76_wr(dev, MT_TX_PWR_CFG_0,
mt76_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
mt76_wr(dev, MT_TX_PWR_CFG_1,
mt76_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[4]));
mt76_wr(dev, MT_TX_PWR_CFG_2,
mt76_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
mt76_wr(dev, MT_TX_PWR_CFG_3,
mt76_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
mt76_wr(dev, MT_TX_PWR_CFG_4,
mt76_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
mt76_wr(dev, MT_TX_PWR_CFG_7,
mt76_tx_power_mask(t.ofdm[4], t.vht[8], t.ht[6], t.vht[8]));
mt76_wr(dev, MT_TX_PWR_CFG_8,
mt76_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
mt76_wr(dev, MT_TX_PWR_CFG_9,
mt76_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
}
static bool
@@ -529,7 +553,6 @@ int mt76_phy_set_channel(struct mt76_dev *dev,
mt76_phy_set_txpower_regs(dev, band);
mt76_configure_tx_delay(dev, band, bw);
mt76_phy_set_txpower(dev);
mt76_apply_rate_power_table(dev);
mt76_set_rx_chains(dev);
mt76_phy_set_band(dev, chan->band, ch_group_index & 1);