mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 21:36:52 +00:00
Ryder LeeandFelix Fietkau
c6b002bcdf
Add support for the MediaTek latest generation IEEE 802.11ax 4x4 device MT7915E, which supports concurrent dual-band operation at both 5GHz and 2.4GHz. Note that this patch just add basic part and will add more HE capabilities support in the further patches. The driver supports AP, Station, Mesh and monitor mode. Signed-off-by: Ryder Lee <[email protected]> Signed-off-by: Shayne Chen <[email protected]> Signed-off-by: Chih-Min Chen <[email protected]> Suggested-by: Shihwei Lin <[email protected]> Tested-by: Evelyn Tsai <[email protected]> Acked-by: Yiwei Chung <[email protected]> Acked-by: YF Luo <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
286 lines
7.4 KiB
C
286 lines
7.4 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc. */
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#include "mt7915.h"
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#include "../dma.h"
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#include "mac.h"
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static int
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mt7915_init_tx_queues(struct mt7915_dev *dev, int n_desc)
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{
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struct mt76_sw_queue *q;
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struct mt76_queue *hwq;
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int err, i;
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hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
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if (!hwq)
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return -ENOMEM;
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err = mt76_queue_alloc(dev, hwq, MT7915_TXQ_BAND0, n_desc, 0,
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MT_TX_RING_BASE);
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if (err < 0)
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return err;
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for (i = 0; i < MT_TXQ_MCU; i++) {
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q = &dev->mt76.q_tx[i];
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INIT_LIST_HEAD(&q->swq);
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q->q = hwq;
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}
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return 0;
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}
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static int
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mt7915_init_mcu_queue(struct mt7915_dev *dev, struct mt76_sw_queue *q,
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int idx, int n_desc)
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{
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struct mt76_queue *hwq;
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int err;
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hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
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if (!hwq)
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return -ENOMEM;
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err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
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if (err < 0)
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return err;
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INIT_LIST_HEAD(&q->swq);
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q->q = hwq;
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return 0;
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}
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void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb)
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{
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struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
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__le32 *rxd = (__le32 *)skb->data;
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enum rx_pkt_type type;
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type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
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switch (type) {
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case PKT_TYPE_TXRX_NOTIFY:
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mt7915_mac_tx_free(dev, skb);
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break;
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case PKT_TYPE_RX_EVENT:
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mt7915_mcu_rx_event(dev, skb);
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break;
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case PKT_TYPE_NORMAL:
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if (!mt7915_mac_fill_rx(dev, skb)) {
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mt76_rx(&dev->mt76, q, skb);
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return;
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}
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/* fall through */
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default:
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dev_kfree_skb(skb);
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break;
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}
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}
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static int mt7915_poll_tx(struct napi_struct *napi, int budget)
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{
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static const u8 queue_map[] = {
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MT_TXQ_MCU,
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MT_TXQ_MCU_WA,
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MT_TXQ_BE
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};
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struct mt7915_dev *dev;
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int i;
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dev = container_of(napi, struct mt7915_dev, mt76.tx_napi);
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for (i = 0; i < ARRAY_SIZE(queue_map); i++)
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mt76_queue_tx_cleanup(dev, queue_map[i], false);
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if (napi_complete_done(napi, 0))
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mt7915_irq_enable(dev, MT_INT_TX_DONE_ALL);
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for (i = 0; i < ARRAY_SIZE(queue_map); i++)
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mt76_queue_tx_cleanup(dev, queue_map[i], false);
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mt7915_mac_sta_poll(dev);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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return 0;
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}
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void mt7915_dma_prefetch(struct mt7915_dev *dev)
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{
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#define PREFETCH(base, depth) ((base) << 16 | (depth))
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mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x40, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x80, 0x0));
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mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL, PREFETCH(0x80, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL, PREFETCH(0xc0, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL, PREFETCH(0x100, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL, PREFETCH(0x140, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL, PREFETCH(0x180, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL, PREFETCH(0x1c0, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL, PREFETCH(0x200, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL, PREFETCH(0x240, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL, PREFETCH(0x280, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL, PREFETCH(0x2c0, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL, PREFETCH(0x300, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL, PREFETCH(0x340, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL, PREFETCH(0x380, 0x4));
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mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL, PREFETCH(0x3c0, 0x0));
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mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL, PREFETCH(0x3c0, 0x4));
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mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL, PREFETCH(0x400, 0x4));
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mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL, PREFETCH(0x440, 0x4));
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mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL, PREFETCH(0x480, 0x0));
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}
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int mt7915_dma_init(struct mt7915_dev *dev)
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{
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/* Increase buffer size to receive large VHT/HE MPDUs */
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int rx_buf_size = MT_RX_BUF_SIZE * 2;
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int ret;
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mt76_dma_attach(&dev->mt76);
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/* configure global setting */
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mt76_set(dev, MT_WFDMA1_GLO_CFG,
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MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
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/* configure perfetch settings */
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mt7915_dma_prefetch(dev);
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/* reset dma idx */
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
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mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
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/* configure delay interrupt */
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
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mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
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/* init tx queue */
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ret = mt7915_init_tx_queues(dev, MT7915_TX_RING_SIZE);
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if (ret)
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return ret;
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/* command to WM */
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ret = mt7915_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7915_TXQ_MCU_WM,
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MT7915_TX_MCU_RING_SIZE);
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if (ret)
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return ret;
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/* command to WA */
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ret = mt7915_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU_WA],
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MT7915_TXQ_MCU_WA,
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MT7915_TX_MCU_RING_SIZE);
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if (ret)
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return ret;
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/* firmware download */
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ret = mt7915_init_mcu_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
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MT7915_TXQ_FWDL,
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MT7915_TX_FWDL_RING_SIZE);
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if (ret)
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return ret;
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/* event from WM */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
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MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE,
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rx_buf_size, MT_RX_EVENT_RING_BASE);
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if (ret)
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return ret;
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/* event from WA */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
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MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE,
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rx_buf_size, MT_RX_EVENT_RING_BASE);
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if (ret)
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return ret;
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/* rx data */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
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MT7915_RX_RING_SIZE, rx_buf_size,
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MT_RX_DATA_RING_BASE);
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if (ret)
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return ret;
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ret = mt76_init_queues(dev);
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if (ret < 0)
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return ret;
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netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
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mt7915_poll_tx, NAPI_POLL_WEIGHT);
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napi_enable(&dev->mt76.tx_napi);
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/* hif wait WFDMA idle */
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mt76_set(dev, MT_WFDMA0_BUSY_ENA,
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MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_BUSY_ENA_RX_FIFO);
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mt76_set(dev, MT_WFDMA1_BUSY_ENA,
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MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA1_BUSY_ENA_RX_FIFO);
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mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA,
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
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mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA,
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MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
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mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
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MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
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/* set WFDMA Tx/Rx */
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
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mt76_set(dev, MT_WFDMA1_GLO_CFG,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
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/* enable interrupts for TX/RX rings */
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mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_MCU_CMD);
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return 0;
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}
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void mt7915_dma_cleanup(struct mt7915_dev *dev)
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{
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/* disable */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN);
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mt76_clear(dev, MT_WFDMA1_GLO_CFG,
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MT_WFDMA1_GLO_CFG_TX_DMA_EN |
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MT_WFDMA1_GLO_CFG_RX_DMA_EN);
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/* reset */
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mt76_clear(dev, MT_WFDMA1_RST,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA1_RST,
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MT_WFDMA1_RST_DMASHDL_ALL_RST |
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MT_WFDMA1_RST_LOGIC_RST);
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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tasklet_kill(&dev->mt76.tx_tasklet);
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mt76_dma_cleanup(&dev->mt76);
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}
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