mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Ethan Nelson-MooreandFelix Fietkau
d88989f8c6
A small piece of code in mt7925/regs.h depends on CONFIG_MT76_DEV, which has never been defined in the kernel. Remove this dead code. Discovered while searching for CONFIG_* symbols referenced in code but not defined in any Kconfig file. Signed-off-by: Ethan Nelson-Moore <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Felix Fietkau <[email protected]>
140 lines
5.1 KiB
C
140 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
|
|
/* Copyright (C) 2023 MediaTek Inc. */
|
|
|
|
#ifndef __MT7925_REGS_H
|
|
#define __MT7925_REGS_H
|
|
|
|
#include "../mt792x_regs.h"
|
|
|
|
#define MT_MDP_BASE 0x820cc800
|
|
#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
|
|
|
|
#define MT_MDP_DCR0 MT_MDP(0x000)
|
|
#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
|
|
#define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
|
|
|
|
#define MT_MDP_DCR1 MT_MDP(0x004)
|
|
#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
|
|
|
|
#define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8))
|
|
#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
|
|
#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
|
|
#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
|
|
|
|
#define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8))
|
|
#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
|
|
#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
|
|
#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
|
|
#define MT_MDP_TO_HIF 0
|
|
#define MT_MDP_TO_WM 1
|
|
|
|
#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
|
|
#define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
|
|
#define HOST_RX_DONE_INT_ENA4 BIT(12)
|
|
#define HOST_RX_DONE_INT_ENA5 BIT(13)
|
|
#define HOST_RX_DONE_INT_ENA6 BIT(14)
|
|
#define HOST_RX_DONE_INT_ENA7 BIT(15)
|
|
#define HOST_RX_DONE_INT_ENA8 BIT(16)
|
|
#define HOST_RX_DONE_INT_ENA9 BIT(17)
|
|
#define HOST_RX_DONE_INT_ENA10 BIT(18)
|
|
#define HOST_RX_DONE_INT_ENA11 BIT(19)
|
|
#define HOST_TX_DONE_INT_ENA15 BIT(25)
|
|
#define HOST_TX_DONE_INT_ENA16 BIT(26)
|
|
#define HOST_TX_DONE_INT_ENA17 BIT(27)
|
|
|
|
/* WFDMA interrupt */
|
|
#define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA1
|
|
|
|
#define MT7925_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2
|
|
#define MT7925_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0
|
|
#define MT7925_INT_RX_DONE_ALL (MT7925_INT_RX_DONE_DATA | \
|
|
MT7925_INT_RX_DONE_WM | \
|
|
MT_INT_RX_DONE_WM2)
|
|
|
|
#define MT7927_INT_RX_DONE_DATA MT7927_RX_DONE_INT_ENA4
|
|
#define MT7927_INT_RX_DONE_WM MT7927_RX_DONE_INT_ENA6
|
|
#define MT7927_INT_RX_DONE_WM2 MT7927_RX_DONE_INT_ENA7
|
|
#define MT7927_INT_RX_DONE_ALL (MT7927_INT_RX_DONE_DATA | \
|
|
MT7927_INT_RX_DONE_WM | \
|
|
MT7927_INT_RX_DONE_WM2)
|
|
|
|
#define MT7928_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA0
|
|
#define MT7928_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA3
|
|
#define MT7928_INT_RX_DONE_ALL (MT7928_INT_RX_DONE_DATA | \
|
|
MT7928_INT_RX_DONE_WM | \
|
|
MT_INT_RX_DONE_WM2)
|
|
|
|
#define MT_INT_TX_DONE_MCU_WM (HOST_TX_DONE_INT_ENA15 | \
|
|
HOST_TX_DONE_INT_ENA17)
|
|
|
|
#define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16
|
|
#define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0
|
|
|
|
#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \
|
|
MT_INT_TX_DONE_FWDL)
|
|
#define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU | \
|
|
MT_INT_TX_DONE_BAND0 | \
|
|
GENMASK(18, 4))
|
|
|
|
#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
|
|
|
|
#define MT_INFRA_CFG_BASE 0xd1000
|
|
#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
|
|
|
|
#define MT_HIF_REMAP_L1 0x155024
|
|
#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)
|
|
#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
|
|
#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
|
|
#define MT_HIF_REMAP_BASE_L1 0x130000
|
|
|
|
#define MT_HIF_REMAP_L2 0x0120
|
|
#define MT_HIF_REMAP_BASE_L2 0x18500000
|
|
|
|
#define MT_WFSYS_SW_RST_B 0x7c000140
|
|
|
|
#define MT7925_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
|
|
#define MT7928_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x400)
|
|
#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
|
|
|
|
#define MT7925_WTBL_UPDATE MT_WTBLON_TOP(0x380)
|
|
#define MT7928_WTBL_UPDATE MT_WTBLON_TOP(0x410)
|
|
#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
|
|
#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14)
|
|
|
|
#define MT7928_WTBL_ITCR MT_WTBLON_TOP(0x440)
|
|
#define MT7928_WTBL_ITDR0 MT_WTBLON_TOP(0x448)
|
|
#define MT7928_WTBL_ITDR1 MT_WTBLON_TOP(0x44c)
|
|
|
|
#define MT7925_PCIE_MAC_BASE 0x10000
|
|
#define MT7925_PCIE_MAC(ofs) (MT7925_PCIE_MAC_BASE + (ofs))
|
|
#define MT7925_PCIE_MAC_INT_ENABLE MT7925_PCIE_MAC(0x188)
|
|
#define MT7925_PCIE_MAC_PM MT7925_PCIE_MAC(0x194)
|
|
|
|
#define MT7928_PCIE_MAC_BASE 0x74040000
|
|
#define MT7928_PCIE_MAC(ofs) (MT7928_PCIE_MAC_BASE + (ofs))
|
|
#define MT7928_PCIE_MAC_INT_ENABLE MT7928_PCIE_MAC(0x188)
|
|
#define MT7928_PCIE_MAC_PM MT7928_PCIE_MAC(0x194)
|
|
|
|
#define MT_DMASHDL_LITE_BASE 0x20026200
|
|
#define MT_DMASHDL_LITE(ofs) (MT_DMASHDL_LITE_BASE + (ofs))
|
|
#define MT_DMASHDL_LITE_MAIN_CONTROL MT_DMASHDL_LITE(0x004)
|
|
#define MT_DMASHDL_LITE_MAIN_CONTROL_SW_RST BIT(18)
|
|
#define MT_DMASHDL_LITE_PAGE_SIZE MT_DMASHDL_LITE(0x008)
|
|
#define MT_DMASHDL_LITE_PLE_PAGE_SIZE_MASK GENMASK(12, 0)
|
|
#define MT_DMASHDL_LITE_PSE_PAGE_SIZE_MASK GENMASK(28, 16)
|
|
#define MT_DMASHDL_LITE_PKT_MAX_SIZE MT_DMASHDL_LITE(0x00c)
|
|
#define MT_DMASHDL_LITE_PLE_PKT_MAX_SIZE_MASK GENMASK(12, 0)
|
|
#define MT_DMASHDL_LITE_PSE_PKT_MAX_SIZE_MASK GENMASK(28, 16)
|
|
#define MT_DMASHDL_LITE_GROUP_DISABLE0 MT_DMASHDL_LITE(0x010)
|
|
#define MT_DMASHDL_LITE_GROUP_DISABLE1 MT_DMASHDL_LITE(0x014)
|
|
#define MT_DMASHDL_LITE_GROUP_SN_CHK0 MT_DMASHDL_LITE(0x018)
|
|
#define MT_DMASHDL_LITE_GROUP_SN_CHK1 MT_DMASHDL_LITE(0x01c)
|
|
#define MT_DMASHDL_LITE_GROUP_UDF_CHK0 MT_DMASHDL_LITE(0x020)
|
|
#define MT_DMASHDL_LITE_GROUP_UDF_CHK1 MT_DMASHDL_LITE(0x024)
|
|
#define MT_DMASHDL_LITE_Q_MAPPING0 MT_DMASHDL_LITE(0x028)
|
|
#define MT_DMASHDL_LITE_GROUP0_QUOTA MT_DMASHDL_LITE(0x100)
|
|
#define MT_DMASHDL_LITE_GROUP_MIN_QUOTA_MASK GENMASK(12, 0)
|
|
#define MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK GENMASK(28, 16)
|
|
|
|
#endif
|