mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Stella LiuandFelix Fietkau
b51cd50b20
The committed CRB timeline carried a local_map_id byte that does not
exist in the firmware NAN_SCHEDULE_TIMELINE_T layout (map id plus 3
reserved bytes), shifting the availability bitmap. Drop it and match
the firmware structure.
The common-slot check is also dropped as redundant: mac80211 already
tracks common slots, so avail_map is built directly from the peer
schedule.
Fixes: 0f3605e4f8de ("wifi: mt76: mt7925: wire up NAN operations")
Co-developed-by: Sean Wang <[email protected]>
Signed-off-by: Sean Wang <[email protected]>
Signed-off-by: Stella Liu <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Felix Fietkau <[email protected]>
421 lines
9.6 KiB
C
421 lines
9.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/* Copyright (C) 2025-2026 MediaTek Inc. */
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#ifndef __MT7925_NAN_H
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#define __MT7925_NAN_H
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#include <linux/if_ether.h>
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#include <linux/types.h>
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#include "../mt76_connac_mcu.h"
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#define NAN_MAX_SOCIAL_CHANNELS 3
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#define NAN_ANCHOR_MASTER_RANK_NUM 8
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#define NAN_5G_LOW_DISC_CHANNEL 44
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#define NAN_5G_HIGH_DISC_CHANNEL 149
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#define NAN_MAX_MASTER_PREFERENCE 255
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#define NAN_DEFAULT_DW_INTERVAL 1
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#define NAN_DEFAULT_DISC_BCN_INTERVAL 100
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#define NAN_TOTAL_DW 16
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#define NAN_SUPPORTED_2G_FAW_CH_NUM 4
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#define NAN_SUPPORTED_5G_FAW_CH_NUM 4
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#define NAN_TIMELINE_MGMT_SIZE 2
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#define NAN_TIMELINE_MGMT_CHNL_LIST_NUM \
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((NAN_SUPPORTED_2G_FAW_CH_NUM + \
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NAN_SUPPORTED_5G_FAW_CH_NUM) / NAN_TIMELINE_MGMT_SIZE)
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#define NAN_NUM_AVAIL_DB 2
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#define NAN_NDC_ATTRIBUTE_ID_LENGTH 6
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#define NAN_MAX_CONN_CFG 8
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#define NAN_MAX_NDP_CXT 4
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#define MT7925_NAN_CONF_MAX_SIZE \
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(sizeof(struct mt7925_nan_common_hdr) + \
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sizeof(struct mt7925_nan_master_preference_tlv) + \
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sizeof(struct mt7925_nan_dw_interval_tlv) + \
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sizeof(struct mt7925_nan_cluster_id_tlv) + \
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sizeof(struct mt7925_nan_sync_rssi_tlv))
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#define MT7925_NAN_AVAIL_MAX_SIZE \
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(sizeof(struct mt7925_nan_common_hdr) + \
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sizeof(struct mt7925_nan_avail_ctrl_tlv) + \
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sizeof(struct mt7925_nan_avail_entry_tlv))
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#define MT7925_NAN_PEER_MAX_SIZE \
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(sizeof(struct mt7925_nan_common_hdr) + \
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sizeof(struct mt7925_nan_sched_manage_peer_rec_tlv) + \
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sizeof(struct mt7925_nan_sched_update_peer_cap_tlv) + \
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sizeof(struct mt7925_nan_sched_update_crb_tlv))
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/* NAN Availability Attribute */
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#define NAN_AVAIL_ATTR_ID_OFFSET 0
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#define NAN_AVAIL_ATTR_LEN_OFFSET 1
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#define NAN_AVAIL_SEQ_ID_OFFSET 3
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#define NAN_AVAIL_ATTR_CTRL_OFFSET 4
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/* NAN Availability Attribute - Attribute Control Field */
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#define NAN_AVAIL_CTRL_MAPID GENMASK(3, 0)
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#define NAN_AVAIL_CTRL_COMMIT_CHANGED BIT(4)
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#define NAN_AVAIL_CTRL_POTN_CHANGED BIT(5)
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#define NAN_AVAIL_CTRL_PUBLIC_AVAIL_CHANGED BIT(6)
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#define NAN_AVAIL_CTRL_NDC_CHANGED BIT(7)
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#define NAN_AVAIL_CTRL_CHECK_FOR_CHANGED GENMASK(7, 4)
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#define UNII1_LOWER_BOUND 36
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#define UNII1_UPPER_BOUND 50
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#define UNII3_LOWER_BOUND 149
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#define UNII3_UPPER_BOUND 165
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#define NAN_BSS_INDEX_BAND0 0
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enum nan_uni_cmd_tag {
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NAN_UNI_CMD_SET_MASTER_PREFERENCE = 0,
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NAN_UNI_CMD_ENABLE_REQUEST = 7,
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NAN_UNI_CMD_DISABLE_REQUEST = 8,
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NAN_UNI_CMD_UPDATE_AVAILABILITY = 9,
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NAN_UNI_CMD_UPDATE_CRB = 10,
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NAN_UNI_CMD_MANAGE_PEER_SCH_RECORD = 12,
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NAN_UNI_CMD_MAP_STA_RECORD = 13,
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NAN_UNI_CMD_UPDATE_AVAILABILITY_CTRL = 20,
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NAN_UNI_CMD_UPDATE_PEER_CAPABILITY = 21,
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NAN_UNI_CMD_CHANGE_NMI_ADDRESS = 24,
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NAN_UNI_CMD_SET_DW_INTERVAL = 26,
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NAN_UNI_CMD_SET_SYNC_RSSI = 39,
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NAN_UNI_CMD_SET_CLUSTER_ID = 40,
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NAN_UNI_CMD_KEY_MANAGEMENT = 53,
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};
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enum nan_uni_event_tag {
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NAN_UNI_EVENT_ID_DE_EVENT_IND = 19,
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NAN_UNI_EVENT_REPORT_DW_END = 60,
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};
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enum nan_disc_event_type {
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NAN_EVENT_ID_DISC_MAC_ADDR = 0,
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NAN_EVENT_ID_JOINED_CLUSTER = 2,
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};
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/* NAN 4.0 Table 79. Device Capability attribute format, Supported Bands */
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enum nan_supported_bands {
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NAN_SUPPORTED_BAND_ID_2P4G = 2,
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NAN_SUPPORTED_BAND_ID_5G = 4,
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NAN_PROPRIETARY_BAND_ID_6G = 6,
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NAN_SUPPORTED_BAND_ID_6G = 7,
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};
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enum nan_peer_supported_bands {
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NAN_SUPPORTED_BN_2G = 0,
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NAN_SUPPORTED_BN_5G_LOW,
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NAN_SUPPORTED_BN_5G_HIGH,
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NAN_SUPPORTED_BN_6G,
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NAN_SUPPORTED_BN_NUM
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};
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#define NAN_CH_CTRL_OP_CLASS GENMASK(15, 8)
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#define NAN_CH_CTRL_PRIMARY_CH GENMASK(23, 16)
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#define NAN_CRB_USE_DATA_PATH BIT(0)
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#define NAN_CRB_AVAIL_6G_FORMAT GENMASK(2, 1)
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struct mt7925_nan_social_ch_scan_params {
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u8 dwell_time[NAN_MAX_SOCIAL_CHANNELS];
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__le16 scan_period[NAN_MAX_SOCIAL_CHANNELS];
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} __packed;
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/* Firmware-reported NAN device information */
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struct nan_dev_info_evt {
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u8 is_enabled;
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u8 my_addr[ETH_ALEN];
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u8 en_fw_election;
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__le32 nan_dev_role;
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__le32 nan_dev_state;
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u8 mst_preference;
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u8 random_factor;
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u8 cnt_hop;
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u8 cluster_id[ETH_ALEN];
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u8 anchor_mst_addr[ETH_ALEN];
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u8 am_preference;
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u8 am_random_factor;
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u8 parent_mac[ETH_ALEN];
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u8 parent_am_preference;
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u8 parent_am_factor;
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__le32 ambtt;
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__le32 tsf[2];
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u8 pn_igtk[6];
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u8 pn_bigtk[6];
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};
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/* Firmware NAN discovery window event */
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struct nan_rpt_dw_evt {
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struct nan_dev_info_evt device_info;
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__le32 expected_tsf_h;
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__le32 expected_tsf_l;
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__le32 actual_tsf_h;
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__le32 actual_tsf_l;
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__le16 channel;
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__le16 dw_num;
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};
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struct mt7925_nan_conf_dw {
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u8 config_2dot4g_dw_band;
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__le32 dw_2dot4g_interval_val;
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u8 config_5g_dw_band;
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__le32 dw_5g_interval_val;
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} __packed;
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struct mt7925_nan_enable_req_tlv {
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__le16 tag;
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__le16 len;
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u8 master_pref;
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__le16 cluster_low;
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__le16 cluster_high;
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u8 config_support_5g;
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u8 support_5g_val;
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u8 config_sid_beacon;
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u8 sid_beacon_val;
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u8 config_2dot4g_rssi_close;
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u8 rssi_close_2dot4g_val;
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u8 config_2dot4g_rssi_middle;
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u8 rssi_middle_2dot4g_val;
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u8 config_2dot4g_rssi_proximity;
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u8 rssi_proximity_2dot4g_val;
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u8 config_hop_count_limit;
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u8 hop_count_limit_val;
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u8 config_2dot4g_support;
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u8 support_2dot4g_val;
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u8 config_2dot4g_beacons;
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u8 beacon_2dot4g_val;
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u8 config_2dot4g_sdf;
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u8 sdf_2dot4g_val;
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u8 config_5g_beacons;
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u8 beacon_5g_val;
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u8 config_5g_sdf;
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u8 sdf_5g_val;
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u8 config_5g_rssi_close;
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u8 rssi_close_5g_val;
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u8 config_5g_rssi_middle;
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u8 rssi_middle_5g_val;
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u8 config_5g_rssi_close_proximity;
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u8 rssi_close_proximity_5g_val;
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u8 config_rssi_window_size;
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u8 rssi_window_size_val;
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u8 config_oui;
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__le32 oui_val;
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u8 config_intf_addr;
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u8 intf_addr_val[ETH_ALEN];
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u8 config_cluster_attribute_val;
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u8 config_scan_params;
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struct mt7925_nan_social_ch_scan_params scan_params_val;
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u8 config_random_factor_force;
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u8 random_factor_force_val;
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u8 config_hop_count_force;
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u8 hop_count_force_val;
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u8 config_24g_channel;
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__le32 channel_24g_val;
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u8 config_5g_channel;
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__le32 channel_5g_val;
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struct mt7925_nan_conf_dw config_dw;
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u8 config_disc_mac_addr_randomization;
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__le32 disc_mac_addr_rand_interval_sec;
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u8 discovery_indication_cfg;
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u8 config_subscribe_sid_beacon;
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__le32 subscribe_sid_beacon_val;
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u8 enable_log_slot_statistics;
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} __packed __aligned(4);
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struct mt7925_nan_common_hdr {
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u8 reserved[4];
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};
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struct mt7925_nan_master_preference_tlv {
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__le16 tag;
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__le16 len;
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u8 master_preference;
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u8 reserved[3];
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} __packed __aligned(4);
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struct mt7925_nan_dw_interval_tlv {
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__le16 tag;
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__le16 len;
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u8 dw_interval;
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u8 vendor_ioctl;
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__le16 disc_bcn_interval;
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} __packed __aligned(4);
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struct mt7925_nan_cluster_id_tlv {
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__le16 tag;
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__le16 len;
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u8 cluster_id[ETH_ALEN];
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u8 reserved[2];
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} __packed __aligned(4);
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struct mt7925_nan_sync_rssi_tlv {
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__le16 tag;
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__le16 len;
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s8 rssi_close_2g;
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s8 rssi_middle_2g;
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s8 rssi_close_5g;
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s8 rssi_middle_5g;
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} __packed __aligned(4);
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struct mt7925_nan_de_event {
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u8 event_type;
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u8 cluster_id[ETH_ALEN];
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u8 anchor_master_rank[NAN_ANCHOR_MASTER_RANK_NUM];
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u8 own_nmi[ETH_ALEN];
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u8 master_nmi[ETH_ALEN];
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};
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struct mt7925_nan_nmi_addr_tlv {
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__le16 tag;
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__le16 len;
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u8 nmi_addr[ETH_ALEN];
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} __packed __aligned(4);
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struct mt7925_nan_avail_ctrl_tlv {
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__le16 tag;
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__le16 len;
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__le16 avail_ctrl;
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u8 seq_id;
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u8 reserved[1];
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} __packed __aligned(4);
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struct mt7925_nan_ch_timeline {
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u8 is_valid;
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u8 reserved[3];
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__le32 ch_info;
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__le32 num;
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__le32 avail_map[NAN_TOTAL_DW];
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};
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struct mt7925_nan_avail_entry_tlv {
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__le16 tag;
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__le16 len;
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u8 map_id;
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u8 is_cond_avail;
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u8 timeline_idx;
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u8 is_multi_map;
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struct mt7925_nan_ch_timeline ch_list[NAN_TIMELINE_MGMT_CHNL_LIST_NUM];
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} __packed __aligned(4);
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struct mt7925_nan_sched_manage_peer_rec_tlv {
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__le16 tag;
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__le16 len;
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__le32 sch_idx;
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u8 is_activate;
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u8 nmi_addr[ETH_ALEN];
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u8 reserved[1];
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} __packed __aligned(4);
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struct mt7925_nan_sched_update_peer_cap_tlv {
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__le16 tag;
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__le16 len;
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__le32 sch_idx;
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u8 supported_bands;
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__le16 max_chnl_switch_time;
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u8 peer_supported_bands;
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} __packed __aligned(4);
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struct mt7925_nan_sched_timeline {
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u8 map_id;
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u8 reserved[3];
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union {
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__le32 avail_map[NAN_TOTAL_DW];
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u8 avail_block[NAN_TOTAL_DW * 4];
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};
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};
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struct mt7925_nan_sched_faw_ndc_timeline {
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__le32 avail_map[NAN_TOTAL_DW];
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};
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struct mt7925_nan_sched_ndc_ctrl {
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u8 is_valid;
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u8 ndc_id[NAN_NDC_ATTRIBUTE_ID_LENGTH];
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u8 ndc_idx;
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struct mt7925_nan_sched_timeline timeline[NAN_NUM_AVAIL_DB];
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};
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struct mt7925_nan_sched_update_crb_tlv {
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__le16 tag;
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__le16 len;
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__le32 sch_idx;
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u8 flags;
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u8 is_use_ranging;
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u8 reserved[2];
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struct mt7925_nan_sched_timeline comm_ranging_timeline[NAN_TIMELINE_MGMT_SIZE];
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struct mt7925_nan_sched_timeline comm_faw_timeline[NAN_TIMELINE_MGMT_SIZE];
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struct mt7925_nan_sched_ndc_ctrl comm_ndc_ctrl;
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struct mt7925_nan_sched_faw_ndc_timeline faw_ndc_timeline[NAN_TIMELINE_MGMT_SIZE];
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} __packed __aligned(4);
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struct mt7925_nan_sched_map_sta_rec_tlv {
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__le16 tag;
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__le16 len;
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u8 nmi_addr[ETH_ALEN];
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u8 sta_rec_idx;
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u8 ndp_ctx_id;
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__le32 role_idx;
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u8 ndi_addr[ETH_ALEN];
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u8 reserved[2];
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} __packed __aligned(4);
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int mt7925_nan_enable(struct ieee80211_vif *vif,
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struct mt792x_dev *dev,
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struct cfg80211_nan_conf *conf);
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int mt7925_nan_disable(struct ieee80211_vif *vif,
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struct mt792x_dev *dev);
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int mt7925_nan_change_configure(struct ieee80211_vif *vif,
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struct mt792x_dev *dev,
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struct cfg80211_nan_conf *conf);
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void mt7925_nan_mcu_event(struct mt792x_dev *dev, struct sk_buff *skb);
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void mt7925_nan_local_sched_changed(struct mt792x_dev *dev,
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struct ieee80211_vif *vif);
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int mt792x_nan_set_peer_schedule(struct mt792x_dev *dev,
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struct ieee80211_sta *sta);
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int mt792x_nan_set_peer_rec(struct mt76_dev *mdev,
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struct ieee80211_sta *sta);
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int mt792x_nan_map_sta_rec(struct mt76_dev *mdev,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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#endif
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