mirror of
https://github.com/outbackdingo/mt76.git
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109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 Felix Fietkau <[email protected]>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "mt7603.h"
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#define MT_PSE_PAGE_SIZE 128
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static u32
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mt7603_ac_queue_mask0(u32 mask)
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{
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u32 ret = 0;
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ret |= GENMASK(3, 0) * !!(mask & BIT(0));
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ret |= GENMASK(8, 5) * !!(mask & BIT(1));
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ret |= GENMASK(13, 10) * !!(mask & BIT(2));
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ret |= GENMASK(19, 16) * !!(mask & BIT(3));
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return ret;
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}
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static void
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mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
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{
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mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
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}
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static void
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mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
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{
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mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
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}
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static void
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mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
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{
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mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
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MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
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mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
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}
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void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, const u8 *mac_addr)
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{
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const void *_mac = mac_addr;
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u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
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mt76_set(dev, addr + 0 * 4,
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MT76_SET(MT_WTBL1_W0_ADDR_HI, get_unaligned_le16(_mac + 4)));
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mt76_set(dev, addr + 1 * 4,
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MT76_SET(MT_WTBL1_W1_ADDR_LO, get_unaligned_le32(_mac)));
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mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
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}
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void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
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{
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int wtbl2_frame = (idx * MT_WTBL2_SIZE) / MT_PSE_PAGE_SIZE;
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int wtbl2_entry = (idx * MT_WTBL2_SIZE) % MT_PSE_PAGE_SIZE;
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int wtbl3_frame = (idx * MT_WTBL3_SIZE) / MT_PSE_PAGE_SIZE;
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int wtbl3_entry = ((idx * MT_WTBL3_SIZE) % MT_PSE_PAGE_SIZE) * 2;
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int wtbl4_frame = (idx * MT_WTBL4_SIZE) / MT_PSE_PAGE_SIZE;
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int wtbl4_entry = (idx * MT_WTBL4_SIZE) % MT_PSE_PAGE_SIZE;
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u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
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int i;
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mt76_wr(dev, addr + 0 * 4,
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MT_WTBL1_W0_RX_CHECK_A2 |
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MT_WTBL1_W0_RX_VALID);
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mt76_wr(dev, addr + 1 * 4, 0);
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mt76_wr(dev, addr + 2 * 4, 0);
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mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
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mt76_wr(dev, addr + 3 * 4,
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MT76_SET(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
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MT76_SET(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
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MT76_SET(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame));
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mt76_wr(dev, addr + 4 * 4,
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MT76_SET(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
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MT76_SET(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
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MT76_SET(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
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mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
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/* Mapped to WTBL2 */
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addr = MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
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/* Clear BA information */
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mt76_wr(dev, addr + (15 * 4), 0);
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mt76_stop_tx_ac(dev, GENMASK(3, 0));
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for (i = 2; i <= 4; i++)
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mt76_wr(dev, addr + (i * 4), 0);
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mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
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mt76_start_tx_ac(dev, GENMASK(3, 0));
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mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
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mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
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mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
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}
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