mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Ryder LeeandFelix Fietkau
c6b002bcdf
Add support for the MediaTek latest generation IEEE 802.11ax 4x4 device MT7915E, which supports concurrent dual-band operation at both 5GHz and 2.4GHz. Note that this patch just add basic part and will add more HE capabilities support in the further patches. The driver supports AP, Station, Mesh and monitor mode. Signed-off-by: Ryder Lee <[email protected]> Signed-off-by: Shayne Chen <[email protected]> Signed-off-by: Chih-Min Chen <[email protected]> Suggested-by: Shihwei Lin <[email protected]> Tested-by: Evelyn Tsai <[email protected]> Acked-by: Yiwei Chung <[email protected]> Acked-by: YF Luo <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
344 lines
12 KiB
C
344 lines
12 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7915_REGS_H
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#define __MT7915_REGS_H
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/* MCU WFDMA1 */
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#define MT_MCU_WFDMA1_BASE 0x3000
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#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
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#define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
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#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
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#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
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#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
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#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
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#define MT_PLE_BASE 0x8000
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#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
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#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
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#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
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#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
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#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
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#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
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((n) << 2))
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#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
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#define MT_MDP_BASE 0xf000
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#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
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#define MT_MDP_DCR0 MT_MDP(0x000)
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#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
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#define MT_MDP_DCR1 MT_MDP(0x004)
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#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
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#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
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#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
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#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
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#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
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#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
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#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
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#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
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#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
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#define MT_MDP_TO_HIF 0
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#define MT_MDP_TO_WM 1
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/* TMAC: band 0(0x21000), band 1(0xa1000) */
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#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
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#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
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#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
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#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
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#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
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#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
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#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
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#define MT_IFS_EIFS GENMASK(8, 0)
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#define MT_IFS_RIFS GENMASK(14, 10)
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#define MT_IFS_SIFS GENMASK(22, 16)
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#define MT_IFS_SLOT GENMASK(30, 24)
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#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
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#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
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#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
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#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
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/* DMA Band 0 */
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#define MT_WF_DMA_BASE 0x21e00
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#define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))
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#define MT_DMA_DCR0 MT_WF_DMA(0x000)
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#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
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/* MIB: band 0(0x24800), band 1(0xa4800) */
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#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
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#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
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#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
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#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
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#define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
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#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
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#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
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#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
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#define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098)
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#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
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#define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c)
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#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
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#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
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#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
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#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
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#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
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#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
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#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
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#define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
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#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2))
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#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2))
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#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
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#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
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#define MT_WTBLON_TOP_BASE 0x34000
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#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
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#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
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#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
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#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030)
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#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
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#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
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#define MT_WTBL_UPDATE_BUSY BIT(31)
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#define MT_WTBL_BASE 0x38000
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#define MT_WTBL_LMAC_ID GENMASK(14, 8)
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#define MT_WTBL_LMAC_DW GENMASK(7, 2)
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#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
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FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
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FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
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/* AGG: band 0(0x20800), band 1(0xa0800) */
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#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
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#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
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#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
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#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
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#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
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/* ARB: band 0(0x20c00), band 1(0xa0c00) */
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#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
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#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
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#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
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#define MT_ARB_SCR_TX_DISABLE BIT(8)
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#define MT_ARB_SCR_RX_DISABLE BIT(9)
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/* RMAC: band 0(0x21400), band 1(0xa1400) */
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#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
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#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
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#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
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#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
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#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
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#define MT_WF_RFCR_DROP_VERSION BIT(3)
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#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
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#define MT_WF_RFCR_DROP_MCAST BIT(5)
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#define MT_WF_RFCR_DROP_BCAST BIT(6)
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#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
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#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
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#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
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#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
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#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
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#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
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#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
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#define MT_WF_RFCR_DROP_CTS BIT(14)
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#define MT_WF_RFCR_DROP_RTS BIT(15)
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#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
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#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
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#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
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#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
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#define MT_WF_RFCR_DROP_NDPA BIT(20)
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#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
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#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
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#define MT_WF_RFCR1_DROP_ACK BIT(4)
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#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
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#define MT_WF_RFCR1_DROP_BA BIT(6)
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#define MT_WF_RFCR1_DROP_CFEND BIT(7)
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#define MT_WF_RFCR1_DROP_CFACK BIT(8)
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#define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4)
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#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
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#define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
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#define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8)
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#define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
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#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
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/* WFDMA0 */
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#define MT_WFDMA0_BASE 0xd4000
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#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
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#define MT_WFDMA0_RST MT_WFDMA0(0x100)
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#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
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#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
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#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
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#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
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#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
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#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
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#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
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#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
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#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
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#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
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#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
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#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
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#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
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#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
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#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
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/* WFDMA1 */
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#define MT_WFDMA1_BASE 0xd5000
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#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
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#define MT_WFDMA1_RST MT_WFDMA1(0x100)
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#define MT_WFDMA1_RST_LOGIC_RST BIT(4)
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#define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
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#define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
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#define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
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#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
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#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
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#define MT_MCU_CMD MT_WFDMA1(0x1f0)
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#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
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#define MT_MCU_CMD_STOP_DMA BIT(2)
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#define MT_MCU_CMD_RESET_DONE BIT(3)
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#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
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#define MT_MCU_CMD_NORMAL_STATE BIT(5)
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#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
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#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
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#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
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#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
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#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
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#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
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#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
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#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
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#define MT_TX_RING_BASE MT_WFDMA1(0x300)
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#define MT_RX_EVENT_RING_BASE MT_WFDMA1(0x500)
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#define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600)
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#define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604)
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#define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608)
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#define MT_WFDMA1_TX_RING3_EXT_CTRL MT_WFDMA1(0x60c)
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#define MT_WFDMA1_TX_RING4_EXT_CTRL MT_WFDMA1(0x610)
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#define MT_WFDMA1_TX_RING5_EXT_CTRL MT_WFDMA1(0x614)
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#define MT_WFDMA1_TX_RING6_EXT_CTRL MT_WFDMA1(0x618)
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#define MT_WFDMA1_TX_RING7_EXT_CTRL MT_WFDMA1(0x61c)
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#define MT_WFDMA1_TX_RING16_EXT_CTRL MT_WFDMA1(0x640)
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#define MT_WFDMA1_TX_RING17_EXT_CTRL MT_WFDMA1(0x644)
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#define MT_WFDMA1_TX_RING18_EXT_CTRL MT_WFDMA1(0x648)
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#define MT_WFDMA1_TX_RING19_EXT_CTRL MT_WFDMA1(0x64c)
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#define MT_WFDMA1_TX_RING20_EXT_CTRL MT_WFDMA1(0x650)
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#define MT_WFDMA1_TX_RING21_EXT_CTRL MT_WFDMA1(0x654)
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#define MT_WFDMA1_TX_RING22_EXT_CTRL MT_WFDMA1(0x658)
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#define MT_WFDMA1_TX_RING23_EXT_CTRL MT_WFDMA1(0x65c)
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#define MT_WFDMA1_RX_RING0_EXT_CTRL MT_WFDMA1(0x680)
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#define MT_WFDMA1_RX_RING1_EXT_CTRL MT_WFDMA1(0x684)
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#define MT_WFDMA1_RX_RING2_EXT_CTRL MT_WFDMA1(0x688)
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#define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c)
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/* WFDMA CSR */
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#define MT_WFDMA_EXT_CSR_BASE 0xd7000
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#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
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#define MT_INT_SOURCE_CSR MT_WFDMA_EXT_CSR(0x10)
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#define MT_INT_MASK_CSR MT_WFDMA_EXT_CSR(0x14)
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#define MT_INT_RX_DONE_DATA BIT(16)
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#define MT_INT_RX_DONE_WM BIT(0)
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#define MT_INT_RX_DONE_WA BIT(1)
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#define MT_INT_RX_DONE(_n) ((_n) ? BIT((_n) - 1) : BIT(16))
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#define MT_INT_RX_DONE_ALL (BIT(0) | BIT(1) | BIT(16))
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#define MT_INT_TX_DONE_ALL (BIT(15) | GENMASK(27, 26) | BIT(30))
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#define MT_INT_MCU_CMD BIT(29)
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#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
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#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
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/* WFDMA0 PCIE1 */
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#define MT_WFDMA0_PCIE1_BASE 0xd8000
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#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
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#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
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#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
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#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
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#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
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/* WFDMA1 PCIE1 */
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#define MT_WFDMA1_PCIE1_BASE 0xd9000
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#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
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#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
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#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
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#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
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#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
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#define MT_INFRA_CFG_BASE 0xf1000
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#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
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#define MT_HIF_REMAP_L1 MT_INFRA(0x1ac)
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#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
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#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
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#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
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#define MT_HIF_REMAP_BASE_L1 0xe0000
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#define MT_HIF_REMAP_L2 MT_INFRA(0x1b0)
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#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
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#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
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#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
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#define MT_HIF_REMAP_BASE_L2 0x00000
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#define MT_TOP_BASE 0x18060000
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#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
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#define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
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#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
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#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
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#define MT_TOP_MISC MT_TOP(0xf0)
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#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
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#define MT_HW_BOUND 0x70010020
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#define MT_HW_CHIPID 0x70010200
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#define MT_HW_REV 0x70010204
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#define MT_PCIE_MAC_BASE 0x74030000
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#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
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#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
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/* PHY: band 0(0x83080000), band 1(0x83090000) */
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#define MT_WF_PHY_BASE 0x83080000
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#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
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#define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
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#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
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#endif
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