mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Sean WangandFelix Fietkau
3c2cc90343
It doesn't guarantee the mt7921e gets started with ASPM L0 after each
machine reboot on every platform.
If mt7921e gets started with not ASPM L0, it would be possible that the
driver encounters time to time failure in mt7921_pci_probe, like a
weird chip identifier is read
[ 215.514503] mt7921e 0000:05:00.0: ASIC revision: feed0000
[ 216.604741] mt7921e: probe of 0000:05:00.0 failed with error -110
or failing to init hardware because the driver is not allowed to access the
register until the device is in ASPM L0 state. So, we call
__mt7921e_mcu_drv_pmctrl in early mt7921_pci_probe to force the device
to bring back to the L0 state for we can safely access registers in any
case.
In the patch, we move all functions from dma.c to pci.c and register mt76
bus operation earilier, that is the __mt7921e_mcu_drv_pmctrl depends on.
Fixes: bf3747ae2e25 ("mt76: mt7921: enable aspm by default")
Reported-by: Kai-Chuan Hsieh <[email protected]>
Co-developed-by: Deren Wu <[email protected]>
Signed-off-by: Deren Wu <[email protected]>
Signed-off-by: Sean Wang <[email protected]>
Signed-off-by: Felix Fietkau <[email protected]>
511 lines
14 KiB
C
511 lines
14 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "mt7921.h"
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#include "mac.h"
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#include "mcu.h"
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#include "../trace.h"
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static const struct pci_device_id mt7921_pci_device_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) },
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) },
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) },
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) },
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{ },
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};
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static bool mt7921_disable_aspm;
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module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
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MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
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static void
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mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
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{
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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if (q == MT_RXQ_MAIN)
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mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA);
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else if (q == MT_RXQ_MCU_WA)
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mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2);
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else
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mt7921_irq_enable(dev, MT_INT_RX_DONE_WM);
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}
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static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance)
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{
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struct mt7921_dev *dev = dev_instance;
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
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return IRQ_NONE;
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tasklet_schedule(&dev->irq_tasklet);
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return IRQ_HANDLED;
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}
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static void mt7921_irq_tasklet(unsigned long data)
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{
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struct mt7921_dev *dev = (struct mt7921_dev *)data;
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u32 intr, mask = 0;
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
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intr &= dev->mt76.mmio.irqmask;
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mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
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trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
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mask |= intr & MT_INT_RX_DONE_ALL;
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if (intr & MT_INT_TX_DONE_MCU)
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mask |= MT_INT_TX_DONE_MCU;
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if (intr & MT_INT_MCU_CMD) {
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u32 intr_sw;
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intr_sw = mt76_rr(dev, MT_MCU_CMD);
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/* ack MCU2HOST_SW_INT_STA */
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mt76_wr(dev, MT_MCU_CMD, intr_sw);
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if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
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mask |= MT_INT_RX_DONE_DATA;
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intr |= MT_INT_RX_DONE_DATA;
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}
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}
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mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);
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if (intr & MT_INT_TX_DONE_ALL)
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napi_schedule(&dev->mt76.tx_napi);
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if (intr & MT_INT_RX_DONE_WM)
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napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
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if (intr & MT_INT_RX_DONE_WM2)
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napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
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if (intr & MT_INT_RX_DONE_DATA)
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napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
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}
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static int mt7921e_init_reset(struct mt7921_dev *dev)
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{
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return mt7921_wpdma_reset(dev, true);
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}
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static void mt7921e_unregister_device(struct mt7921_dev *dev)
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{
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int i;
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struct mt76_connac_pm *pm = &dev->pm;
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mt76_unregister_device(&dev->mt76);
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mt76_for_each_q_rx(&dev->mt76, i)
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napi_disable(&dev->mt76.napi[i]);
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cancel_delayed_work_sync(&pm->ps_work);
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cancel_work_sync(&pm->wake_work);
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mt7921_tx_token_put(dev);
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mt7921_mcu_drv_pmctrl(dev);
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mt7921_dma_cleanup(dev);
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mt7921_wfsys_reset(dev);
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mt7921_mcu_exit(dev);
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tasklet_disable(&dev->irq_tasklet);
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mt76_free_device(&dev->mt76);
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}
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static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
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{
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static const struct {
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u32 phys;
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u32 mapped;
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u32 size;
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} fixed_map[] = {
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{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
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{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
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{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
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{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
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{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
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{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
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{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
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{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
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{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
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{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
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{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
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{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
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{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
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{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
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{ 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
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{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
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{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
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{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
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{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
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{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
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{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
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{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
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{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
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{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
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{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
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{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
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{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
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{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
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{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
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{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
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{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
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{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
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{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
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{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
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};
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int i;
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if (addr < 0x100000)
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return addr;
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for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
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u32 ofs;
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if (addr < fixed_map[i].phys)
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continue;
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ofs = addr - fixed_map[i].phys;
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if (ofs > fixed_map[i].size)
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continue;
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return fixed_map[i].mapped + ofs;
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}
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if ((addr >= 0x18000000 && addr < 0x18c00000) ||
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(addr >= 0x70000000 && addr < 0x78000000) ||
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(addr >= 0x7c000000 && addr < 0x7c400000))
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return mt7921_reg_map_l1(dev, addr);
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dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
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addr);
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return 0;
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}
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static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
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{
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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u32 addr = __mt7921_reg_addr(dev, offset);
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return dev->bus_ops->rr(mdev, addr);
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}
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static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
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{
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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u32 addr = __mt7921_reg_addr(dev, offset);
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dev->bus_ops->wr(mdev, addr, val);
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}
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static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
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{
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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u32 addr = __mt7921_reg_addr(dev, offset);
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return dev->bus_ops->rmw(mdev, addr, mask, val);
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}
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static int mt7921_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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static const struct mt76_driver_ops drv_ops = {
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/* txwi_size = txd size + txp size */
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.txwi_size = MT_TXD_SIZE + sizeof(struct mt7921_txp_common),
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.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
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.survey_flags = SURVEY_INFO_TIME_TX |
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SURVEY_INFO_TIME_RX |
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SURVEY_INFO_TIME_BSS_RX,
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.token_size = MT7921_TOKEN_SIZE,
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.tx_prepare_skb = mt7921e_tx_prepare_skb,
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.tx_complete_skb = mt7921e_tx_complete_skb,
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.rx_check = mt7921e_rx_check,
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.rx_skb = mt7921e_queue_rx_skb,
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.rx_poll_complete = mt7921_rx_poll_complete,
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.sta_ps = mt7921_sta_ps,
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.sta_add = mt7921_mac_sta_add,
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.sta_assoc = mt7921_mac_sta_assoc,
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.sta_remove = mt7921_mac_sta_remove,
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.update_survey = mt7921_update_channel,
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};
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static const struct mt7921_hif_ops mt7921_pcie_ops = {
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.init_reset = mt7921e_init_reset,
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.reset = mt7921e_mac_reset,
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.mcu_init = mt7921e_mcu_init,
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.drv_own = mt7921e_mcu_drv_pmctrl,
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.fw_own = mt7921e_mcu_fw_pmctrl,
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};
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struct mt76_bus_ops *bus_ops;
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struct mt7921_dev *dev;
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struct mt76_dev *mdev;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (ret)
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return ret;
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pci_set_master(pdev);
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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return ret;
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ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
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if (ret)
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goto err_free_pci_vec;
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if (mt7921_disable_aspm)
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mt76_pci_disable_aspm(pdev);
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mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops,
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&drv_ops);
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if (!mdev) {
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ret = -ENOMEM;
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goto err_free_pci_vec;
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}
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dev = container_of(mdev, struct mt7921_dev, mt76);
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dev->hif_ops = &mt7921_pcie_ops;
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mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
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tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
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dev->phy.dev = dev;
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dev->phy.mt76 = &dev->mt76.phy;
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dev->mt76.phy.priv = &dev->phy;
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dev->bus_ops = dev->mt76.bus;
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bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
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GFP_KERNEL);
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if (!bus_ops)
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return -ENOMEM;
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bus_ops->rr = mt7921_rr;
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bus_ops->wr = mt7921_wr;
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bus_ops->rmw = mt7921_rmw;
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dev->mt76.bus = bus_ops;
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ret = __mt7921e_mcu_drv_pmctrl(dev);
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if (ret)
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return ret;
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mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
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(mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
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dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
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ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler,
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IRQF_SHARED, KBUILD_MODNAME, dev);
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if (ret)
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goto err_free_dev;
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ret = mt7921_dma_init(dev);
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if (ret)
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goto err_free_irq;
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ret = mt7921_register_device(dev);
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if (ret)
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goto err_free_irq;
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return 0;
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err_free_irq:
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devm_free_irq(&pdev->dev, pdev->irq, dev);
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err_free_dev:
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mt76_free_device(&dev->mt76);
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err_free_pci_vec:
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pci_free_irq_vectors(pdev);
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return ret;
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}
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static void mt7921_pci_remove(struct pci_dev *pdev)
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{
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struct mt76_dev *mdev = pci_get_drvdata(pdev);
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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mt7921e_unregister_device(dev);
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devm_free_irq(&pdev->dev, pdev->irq, dev);
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pci_free_irq_vectors(pdev);
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}
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#ifdef CONFIG_PM
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static int mt7921_pci_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct mt76_dev *mdev = pci_get_drvdata(pdev);
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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struct mt76_connac_pm *pm = &dev->pm;
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int i, err;
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pm->suspended = true;
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cancel_delayed_work_sync(&pm->ps_work);
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cancel_work_sync(&pm->wake_work);
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err = mt7921_mcu_drv_pmctrl(dev);
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if (err < 0)
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goto restore_suspend;
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err = mt76_connac_mcu_set_hif_suspend(mdev, true);
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if (err)
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goto restore_suspend;
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/* always enable deep sleep during suspend to reduce
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* power consumption
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*/
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mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
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napi_disable(&mdev->tx_napi);
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mt76_worker_disable(&mdev->tx_worker);
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mt76_for_each_q_rx(mdev, i) {
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napi_disable(&mdev->napi[i]);
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}
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pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
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/* wait until dma is idle */
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mt76_poll(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
|
|
MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
|
|
|
|
/* put dma disabled */
|
|
mt76_clear(dev, MT_WFDMA0_GLO_CFG,
|
|
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
|
|
|
|
/* disable interrupt */
|
|
mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
|
|
mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
|
|
synchronize_irq(pdev->irq);
|
|
tasklet_kill(&dev->irq_tasklet);
|
|
|
|
err = mt7921_mcu_fw_pmctrl(dev);
|
|
if (err)
|
|
goto restore_napi;
|
|
|
|
pci_save_state(pdev);
|
|
err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
if (err)
|
|
goto restore_napi;
|
|
|
|
return 0;
|
|
|
|
restore_napi:
|
|
mt76_for_each_q_rx(mdev, i) {
|
|
napi_enable(&mdev->napi[i]);
|
|
}
|
|
napi_enable(&mdev->tx_napi);
|
|
|
|
if (!pm->ds_enable)
|
|
mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
|
|
|
|
mt76_connac_mcu_set_hif_suspend(mdev, false);
|
|
|
|
restore_suspend:
|
|
pm->suspended = false;
|
|
|
|
return err;
|
|
}
|
|
|
|
static int mt7921_pci_resume(struct pci_dev *pdev)
|
|
{
|
|
struct mt76_dev *mdev = pci_get_drvdata(pdev);
|
|
struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
|
|
struct mt76_connac_pm *pm = &dev->pm;
|
|
int i, err;
|
|
|
|
err = pci_set_power_state(pdev, PCI_D0);
|
|
if (err)
|
|
return err;
|
|
|
|
pci_restore_state(pdev);
|
|
|
|
err = mt7921_mcu_drv_pmctrl(dev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
mt7921_wpdma_reinit_cond(dev);
|
|
|
|
/* enable interrupt */
|
|
mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
|
|
mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
|
|
MT_INT_MCU_CMD);
|
|
mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
|
|
|
|
/* put dma enabled */
|
|
mt76_set(dev, MT_WFDMA0_GLO_CFG,
|
|
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
|
|
|
|
mt76_worker_enable(&mdev->tx_worker);
|
|
|
|
local_bh_disable();
|
|
mt76_for_each_q_rx(mdev, i) {
|
|
napi_enable(&mdev->napi[i]);
|
|
napi_schedule(&mdev->napi[i]);
|
|
}
|
|
napi_enable(&mdev->tx_napi);
|
|
napi_schedule(&mdev->tx_napi);
|
|
local_bh_enable();
|
|
|
|
/* restore previous ds setting */
|
|
if (!pm->ds_enable)
|
|
mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
|
|
|
|
err = mt76_connac_mcu_set_hif_suspend(mdev, false);
|
|
if (err)
|
|
return err;
|
|
|
|
pm->suspended = false;
|
|
|
|
return err;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
struct pci_driver mt7921_pci_driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.id_table = mt7921_pci_device_table,
|
|
.probe = mt7921_pci_probe,
|
|
.remove = mt7921_pci_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = mt7921_pci_suspend,
|
|
.resume = mt7921_pci_resume,
|
|
#endif /* CONFIG_PM */
|
|
};
|
|
|
|
module_pci_driver(mt7921_pci_driver);
|
|
|
|
MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
|
|
MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
|
|
MODULE_FIRMWARE(MT7921_ROM_PATCH);
|
|
MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
|
|
MODULE_FIRMWARE(MT7922_ROM_PATCH);
|
|
MODULE_AUTHOR("Sean Wang <[email protected]>");
|
|
MODULE_AUTHOR("Lorenzo Bianconi <[email protected]>");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|