mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Felix Fietkau
99ce686254
The ring is used for looping back tx powersave filtered frames, so it could use some more room, in case more than one aggregate was queued Signed-off-by: Felix Fietkau <[email protected]>
268 lines
6.7 KiB
C
268 lines
6.7 KiB
C
/* SPDX-License-Identifier: ISC */
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#ifndef __MT7603_H
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#define __MT7603_H
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#include <linux/interrupt.h>
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#include <linux/ktime.h>
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#include "../mt76.h"
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#include "regs.h"
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#define MT7603_MAX_INTERFACES 4
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#define MT7603_WTBL_SIZE 128
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#define MT7603_WTBL_RESERVED (MT7603_WTBL_SIZE - 1)
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#define MT7603_WTBL_STA (MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES)
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#define MT7603_RATE_RETRY 2
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#define MT7603_MCU_RX_RING_SIZE 64
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#define MT7603_RX_RING_SIZE 128
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#define MT7603_FIRMWARE_E1 "mt7603_e1.bin"
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#define MT7603_FIRMWARE_E2 "mt7603_e2.bin"
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#define MT7628_FIRMWARE_E1 "mt7628_e1.bin"
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#define MT7628_FIRMWARE_E2 "mt7628_e2.bin"
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#define MT7603_EEPROM_SIZE 1024
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#define MT_AGG_SIZE_LIMIT(_n) (((_n) + 1) * 4)
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#define MT7603_PRE_TBTT_TIME 5000 /* ms */
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#define MT7603_WATCHDOG_TIME 100 /* ms */
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#define MT7603_WATCHDOG_TIMEOUT 10 /* number of checks */
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#define MT7603_EDCCA_BLOCK_TH 10
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#define MT7603_CFEND_RATE_DEFAULT 0x69 /* chip default (24M) */
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#define MT7603_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
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struct mt7603_vif;
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struct mt7603_sta;
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enum {
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MT7603_REV_E1 = 0x00,
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MT7603_REV_E2 = 0x10,
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MT7628_REV_E1 = 0x8a00,
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};
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enum mt7603_bw {
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MT_BW_20,
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MT_BW_40,
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MT_BW_80,
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};
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struct mt7603_rate_set {
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struct ieee80211_tx_rate probe_rate;
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struct ieee80211_tx_rate rates[4];
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};
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struct mt7603_sta {
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struct mt76_wcid wcid; /* must be first */
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struct mt7603_vif *vif;
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struct list_head poll_list;
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u32 tx_airtime_ac[4];
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struct sk_buff_head psq;
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struct ieee80211_tx_rate rates[4];
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struct mt7603_rate_set rateset[2];
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u32 rate_set_tsf;
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u8 rate_count;
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u8 n_rates;
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u8 rate_probe;
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u8 smps;
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u8 ps;
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};
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struct mt7603_vif {
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struct mt7603_sta sta; /* must be first */
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u8 idx;
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};
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enum mt7603_reset_cause {
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RESET_CAUSE_TX_HANG,
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RESET_CAUSE_TX_BUSY,
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RESET_CAUSE_RX_BUSY,
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RESET_CAUSE_BEACON_STUCK,
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RESET_CAUSE_RX_PSE_BUSY,
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RESET_CAUSE_MCU_HANG,
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RESET_CAUSE_RESET_FAILED,
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__RESET_CAUSE_MAX
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};
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struct mt7603_dev {
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union { /* must be first */
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struct mt76_dev mt76;
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struct mt76_phy mphy;
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};
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const struct mt76_bus_ops *bus_ops;
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u32 rxfilter;
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u8 vif_mask;
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struct list_head sta_poll_list;
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spinlock_t sta_poll_lock;
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struct mt7603_sta global_sta;
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u32 agc0, agc3;
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u32 false_cca_ofdm, false_cca_cck;
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unsigned long last_cca_adj;
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u32 ampdu_ref;
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__le32 rx_ampdu_ts;
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u8 rssi_offset[3];
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u8 slottime;
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s16 coverage_class;
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s8 tx_power_limit;
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ktime_t ed_time;
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spinlock_t ps_lock;
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u8 mac_work_count;
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u8 mcu_running;
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u8 ed_monitor_enabled;
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u8 ed_monitor;
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s8 ed_trigger;
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u8 ed_strict_mode;
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u8 ed_strong_signal;
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bool dynamic_sensitivity;
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s8 sensitivity;
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u8 beacon_check;
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u8 tx_hang_check;
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u8 tx_dma_check;
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u8 rx_dma_check;
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u8 rx_pse_check;
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u8 mcu_hang;
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enum mt7603_reset_cause cur_reset_cause;
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u16 tx_dma_idx[4];
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u16 rx_dma_idx;
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u32 reset_test;
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unsigned int reset_cause[__RESET_CAUSE_MAX];
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};
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extern const struct mt76_driver_ops mt7603_drv_ops;
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extern const struct ieee80211_ops mt7603_ops;
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extern struct pci_driver mt7603_pci_driver;
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extern struct platform_driver mt76_wmac_driver;
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static inline bool is_mt7603(struct mt7603_dev *dev)
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{
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return mt76xx_chip(dev) == 0x7603;
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}
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static inline bool is_mt7628(struct mt7603_dev *dev)
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{
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return mt76xx_chip(dev) == 0x7628;
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}
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/* need offset to prevent conflict with ampdu_ack_len */
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#define MT_RATE_DRIVER_DATA_OFFSET 4
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u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr);
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irqreturn_t mt7603_irq_handler(int irq, void *dev_instance);
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int mt7603_register_device(struct mt7603_dev *dev);
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void mt7603_unregister_device(struct mt7603_dev *dev);
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int mt7603_eeprom_init(struct mt7603_dev *dev);
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int mt7603_dma_init(struct mt7603_dev *dev);
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void mt7603_dma_cleanup(struct mt7603_dev *dev);
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int mt7603_mcu_init(struct mt7603_dev *dev);
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void mt7603_init_debugfs(struct mt7603_dev *dev);
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static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask)
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{
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mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
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}
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static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)
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{
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mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
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}
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void mt7603_mac_reset_counters(struct mt7603_dev *dev);
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void mt7603_mac_dma_start(struct mt7603_dev *dev);
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void mt7603_mac_start(struct mt7603_dev *dev);
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void mt7603_mac_stop(struct mt7603_dev *dev);
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void mt7603_mac_work(struct work_struct *work);
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void mt7603_mac_set_timing(struct mt7603_dev *dev);
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void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval);
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int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);
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void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);
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void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid);
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void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
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int ba_size);
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void mt7603_mac_sta_poll(struct mt7603_dev *dev);
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void mt7603_pse_client_reset(struct mt7603_dev *dev);
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int mt7603_mcu_set_channel(struct mt7603_dev *dev);
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int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);
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void mt7603_mcu_exit(struct mt7603_dev *dev);
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void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
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const u8 *mac_addr);
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void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
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void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);
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void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
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struct ieee80211_tx_rate *probe_rate,
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struct ieee80211_tx_rate *rates);
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int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
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struct ieee80211_key_conf *key);
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void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
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bool enabled);
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void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
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bool enabled);
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void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort);
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int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
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enum mt76_txq_id qid, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta,
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struct mt76_tx_info *tx_info);
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void mt7603_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
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struct mt76_queue_entry *e);
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void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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struct sk_buff *skb);
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void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
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void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
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int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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void mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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void mt7603_pre_tbtt_tasklet(unsigned long arg);
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void mt7603_update_channel(struct mt76_dev *mdev);
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void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val);
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void mt7603_cca_stats_reset(struct mt7603_dev *dev);
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void mt7603_init_edcca(struct mt7603_dev *dev);
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#endif
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