mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Lorenzo BianconiandFelix Fietkau
4876740626
mt76_connac2_reverse_frag0_hdr_trans routine is shared between mt7921 and mt7915e drivers. Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
135 lines
2.9 KiB
C
135 lines
2.9 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7921_MAC_H
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#define __MT7921_MAC_H
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#include "../mt76_connac2_mac.h"
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#define MT_CT_PARSE_LEN 72
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#define MT_CT_DMA_BUF_NUM 2
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#define MT_RXD0_LENGTH GENMASK(15, 0)
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#define MT_RXD0_PKT_FLAG GENMASK(19, 16)
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#define MT_RXD0_PKT_TYPE GENMASK(31, 27)
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#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
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#define MT_RXD0_NORMAL_IP_SUM BIT(23)
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#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
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enum rx_pkt_type {
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PKT_TYPE_TXS,
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PKT_TYPE_TXRXV,
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PKT_TYPE_NORMAL,
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PKT_TYPE_RX_DUP_RFB,
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PKT_TYPE_RX_TMR,
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PKT_TYPE_RETRIEVE,
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PKT_TYPE_TXRX_NOTIFY,
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PKT_TYPE_RX_EVENT,
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PKT_TYPE_NORMAL_MCU,
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};
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enum tx_port_idx {
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MT_TX_PORT_IDX_LMAC,
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MT_TX_PORT_IDX_MCU
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};
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enum tx_mcu_port_q_idx {
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MT_TX_MCU_PORT_RX_Q0 = 0x20,
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MT_TX_MCU_PORT_RX_Q1,
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MT_TX_MCU_PORT_RX_Q2,
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MT_TX_MCU_PORT_RX_Q3,
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MT_TX_MCU_PORT_RX_FWDL = 0x3e
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};
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#define MT_CT_INFO_APPLY_TXD BIT(0)
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#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
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#define MT_CT_INFO_MGMT_FRAME BIT(2)
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#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
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#define MT_CT_INFO_HSR2_TX BIT(4)
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#define MT_CT_INFO_FROM_HOST BIT(7)
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#define MT_TXP_MAX_BUF_NUM 6
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struct mt7921_txp {
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__le16 flags;
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__le16 token;
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u8 bss_idx;
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__le16 rept_wds_wcid;
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u8 nbuf;
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__le32 buf[MT_TXP_MAX_BUF_NUM];
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__le16 len[MT_TXP_MAX_BUF_NUM];
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} __packed __aligned(4);
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struct mt7921_tx_free {
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__le16 rx_byte_cnt;
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__le16 ctrl;
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u8 txd_cnt;
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u8 rsv[3];
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__le32 info[];
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} __packed __aligned(4);
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#define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
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#define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
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#define MT_TX_FREE_LATENCY GENMASK(12, 0)
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/* 0: success, others: dropped */
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#define MT_TX_FREE_STATUS GENMASK(14, 13)
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#define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
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#define MT_TX_FREE_PAIR BIT(31)
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/* will support this field in further revision */
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#define MT_TX_FREE_RATE GENMASK(13, 0)
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static inline struct mt7921_txp_common *
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mt7921_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
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{
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u8 *txwi;
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if (!t)
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return NULL;
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txwi = mt76_get_txwi_ptr(dev, t);
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return (struct mt7921_txp_common *)(txwi + MT_TXD_SIZE);
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}
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#define MT_HW_TXP_MAX_MSDU_NUM 4
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#define MT_HW_TXP_MAX_BUF_NUM 4
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#define MT_MSDU_ID_VALID BIT(15)
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#define MT_TXD_LEN_MASK GENMASK(11, 0)
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#define MT_TXD_LEN_MSDU_LAST BIT(14)
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#define MT_TXD_LEN_AMSDU_LAST BIT(15)
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#define MT_TXD_LEN_LAST BIT(15)
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struct mt7921_txp_ptr {
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__le32 buf0;
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__le16 len0;
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__le16 len1;
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__le32 buf1;
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} __packed __aligned(4);
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struct mt7921_hw_txp {
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__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
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struct mt7921_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
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} __packed __aligned(4);
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struct mt7921_txp_common {
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union {
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struct mt7921_hw_txp hw;
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};
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};
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#define MT_WTBL_TXRX_CAP_RATE_OFFSET 7
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#define MT_WTBL_TXRX_RATE_G2_HE 24
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#define MT_WTBL_TXRX_RATE_G2 12
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#define MT_WTBL_AC0_CTT_OFFSET 20
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static inline u32 mt7921_mac_wtbl_lmac_addr(int idx, u8 offset)
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{
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return MT_WTBL_LMAC_OFFS(idx, 0) + offset * 4;
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}
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#endif
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