mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 21:36:52 +00:00
Felix Fietkau
780ea78ba0
It turns out that the code in mt7603_rx_pse_busy() does not detect actual
hardware hangs, it only checks for busy conditions in PSE.
A reset should only be performed if these conditions are true and if there
is no rx activity as well.
Reset the counter whenever a rx interrupt occurs. In order to also deal with
a fully loaded CPU that leaves interrupts disabled with continuous NAPI
polling, also check for pending rx interrupts in the function itself.
Fixes: c8846e101502 ("mt76: add driver for MT7603E and MT7628/7688")
Signed-off-by: Felix Fietkau <[email protected]>
(cherry picked from commit 80b8bcf0e3)
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
// SPDX-License-Identifier: ISC
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#include "mt7603.h"
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#include "../trace.h"
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void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
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{
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struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
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mt7603_irq_enable(dev, MT_INT_RX_DONE(q));
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}
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irqreturn_t mt7603_irq_handler(int irq, void *dev_instance)
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{
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struct mt7603_dev *dev = dev_instance;
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u32 intr;
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intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
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mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
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return IRQ_NONE;
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trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
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intr &= dev->mt76.mmio.irqmask;
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if (intr & MT_INT_MAC_IRQ3) {
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u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3));
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mt76_wr(dev, MT_HW_INT_STATUS(3), hwintr);
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if (hwintr & MT_HW_INT3_PRE_TBTT0)
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tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
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if ((hwintr & MT_HW_INT3_TBTT0) && dev->mt76.csa_complete)
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mt76_csa_finish(&dev->mt76);
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}
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if (intr & MT_INT_TX_DONE_ALL) {
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mt7603_irq_disable(dev, MT_INT_TX_DONE_ALL);
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napi_schedule(&dev->mt76.tx_napi);
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}
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if (intr & MT_INT_RX_DONE(0)) {
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dev->rx_pse_check = 0;
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mt7603_irq_disable(dev, MT_INT_RX_DONE(0));
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napi_schedule(&dev->mt76.napi[0]);
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}
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if (intr & MT_INT_RX_DONE(1)) {
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dev->rx_pse_check = 0;
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mt7603_irq_disable(dev, MT_INT_RX_DONE(1));
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napi_schedule(&dev->mt76.napi[1]);
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}
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return IRQ_HANDLED;
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}
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u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr)
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{
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u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE;
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u32 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
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dev->bus_ops->wr(&dev->mt76, MT_MCU_PCIE_REMAP_2, base);
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return MT_PCIE_REMAP_BASE_2 + offset;
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}
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