mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Felix Fietkau
b5eee1b522
Unlike on earlier chips, DMA completion on MT7615 does not imply actually having sent out any packets. Since AQL will prevent filling the hardware queues and will only allow more packets to be passed to the driver after tx completion, it makes much more sense to schedule the tx tasklet there. This is also needed for scheduling tx in testmode support Signed-off-by: Felix Fietkau <[email protected]>
331 lines
8.3 KiB
C
331 lines
8.3 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2019 MediaTek Inc.
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*
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* Author: Ryder Lee <[email protected]>
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* Roy Luo <[email protected]>
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* Lorenzo Bianconi <[email protected]>
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* Felix Fietkau <[email protected]>
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*/
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#include "mt7615.h"
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#include "../dma.h"
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#include "mac.h"
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static int
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mt7615_init_tx_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q,
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int idx, int n_desc)
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{
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struct mt76_queue *hwq;
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int err;
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hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
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if (!hwq)
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return -ENOMEM;
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err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
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if (err < 0)
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return err;
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INIT_LIST_HEAD(&q->swq);
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q->q = hwq;
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return 0;
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}
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static int
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mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
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{
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static const u8 wmm_queue_map[] = {
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[IEEE80211_AC_BK] = MT7622_TXQ_AC0,
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[IEEE80211_AC_BE] = MT7622_TXQ_AC1,
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[IEEE80211_AC_VI] = MT7622_TXQ_AC2,
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[IEEE80211_AC_VO] = MT7622_TXQ_AC3,
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};
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int ret;
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int i;
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for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[i],
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wmm_queue_map[i],
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MT7615_TX_RING_SIZE / 2);
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if (ret)
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return ret;
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}
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD],
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MT7622_TXQ_MGMT, MT7615_TX_MGMT_RING_SIZE);
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if (ret)
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return ret;
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7622_TXQ_MCU, MT7615_TX_MCU_RING_SIZE);
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return ret;
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}
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static int
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mt7615_init_tx_queues(struct mt7615_dev *dev)
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{
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struct mt76_sw_queue *q;
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int ret, i;
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL],
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MT7615_TXQ_FWDL,
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MT7615_TX_FWDL_RING_SIZE);
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if (ret)
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return ret;
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if (!is_mt7615(&dev->mt76))
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return mt7622_init_tx_queues_multi(dev);
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[0], 0,
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MT7615_TX_RING_SIZE);
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if (ret)
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return ret;
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for (i = 1; i < MT_TXQ_MCU; i++) {
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q = &dev->mt76.q_tx[i];
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INIT_LIST_HEAD(&q->swq);
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q->q = dev->mt76.q_tx[0].q;
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}
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ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
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MT7615_TXQ_MCU,
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MT7615_TX_MCU_RING_SIZE);
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return 0;
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}
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static void
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mt7615_tx_cleanup(struct mt7615_dev *dev)
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{
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int i;
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mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false);
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mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false);
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if (is_mt7615(&dev->mt76)) {
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mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false);
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} else {
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for (i = 0; i < IEEE80211_NUM_ACS; i++)
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mt76_queue_tx_cleanup(dev, i, false);
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}
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}
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static int mt7615_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt7615_dev *dev;
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dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
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mt7615_tx_cleanup(dev);
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if (napi_complete_done(napi, 0))
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mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt7615_tx_cleanup(dev);
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tasklet_schedule(&dev->mt76.tx_tasklet);
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return 0;
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}
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int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
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{
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struct mt76_dev *mdev = &dev->mt76;
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if (!is_mt7663(mdev)) {
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u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
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u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
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if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine busy\n");
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return -EIO;
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}
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return 0;
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}
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if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
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MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine tx busy\n");
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return -EIO;
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}
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if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
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MT_PSE_SRC_CNT, 0, 1000)) {
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dev_err(mdev->dev, "PSE engine busy\n");
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return -EIO;
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}
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if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
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MT_PDMA_BUSY_IDX, 0, 1000)) {
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dev_err(mdev->dev, "PDMA engine busy\n");
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return -EIO;
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}
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return 0;
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}
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static void mt7622_dma_sched_init(struct mt7615_dev *dev)
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{
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u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
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int i;
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mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
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MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
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for (i = 0; i <= 5; i++)
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mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
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mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
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mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
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}
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static void mt7663_dma_sched_init(struct mt7615_dev *dev)
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{
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int i;
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mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
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MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
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FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
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/* enable refill control group 0, 1, 2, 4, 5 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
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/* enable group 0, 1, 2, 4, 5, 15 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
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/* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
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for (i = 0; i < 5; i++)
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
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FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
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/* ALTX0 and ALTX1 QID mapping to group 5 */
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
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mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
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}
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int mt7615_dma_init(struct mt7615_dev *dev)
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{
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int rx_ring_size = MT7615_RX_RING_SIZE;
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int rx_buf_size = MT_RX_BUF_SIZE;
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int ret;
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/* Increase buffer size to receive large VHT MPDUs */
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if (dev->mt76.cap.has_5ghz)
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rx_buf_size *= 2;
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mt76_dma_attach(&dev->mt76);
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mt76_wr(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
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MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
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MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
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mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
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if (is_mt7615(&dev->mt76)) {
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
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mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
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mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
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mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
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mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
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mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
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mt76_set(dev, 0x7158, BIT(16));
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mt76_clear(dev, 0x7000, BIT(23));
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}
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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ret = mt7615_init_tx_queues(dev);
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if (ret)
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return ret;
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/* init rx queues */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
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MT7615_RX_MCU_RING_SIZE, rx_buf_size,
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MT_RX_RING_BASE);
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if (ret)
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return ret;
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if (!is_mt7615(&dev->mt76))
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rx_ring_size /= 2;
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
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rx_ring_size, rx_buf_size, MT_RX_RING_BASE);
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if (ret)
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return ret;
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mt76_wr(dev, MT_DELAY_INT_CFG, 0);
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ret = mt76_init_queues(dev);
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if (ret < 0)
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return ret;
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netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
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mt7615_poll_tx, NAPI_POLL_WEIGHT);
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napi_enable(&dev->mt76.tx_napi);
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mt76_poll(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
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/* start dma engine */
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_EN);
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/* enable interrupts for TX/RX rings */
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mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_MCU_CMD);
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if (is_mt7622(&dev->mt76))
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mt7622_dma_sched_init(dev);
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if (is_mt7663(&dev->mt76))
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mt7663_dma_sched_init(dev);
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return 0;
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}
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void mt7615_dma_cleanup(struct mt7615_dev *dev)
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{
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mt76_clear(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_EN);
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mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
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tasklet_kill(&dev->mt76.tx_tasklet);
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mt76_dma_cleanup(&dev->mt76);
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}
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