mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Felix Fietkau
33f29d2345
MediaTek has asked to switch from the ISC license to BSD-3-Clause-Clear, in order to improve clarity and the legal integrity of the code. The BSD-3-Clause license includes the "no endorsement" clause, which is important for protecting the reputation of the original authors and contributors by preventing unauthorized use of their names for endorsement purposes. This clause is absent in the BSD-2-Clause license, which is more permissive but lacks this specific protection. This change also cleans up the license of some Kconfig/Makefile files, which were accidentally marked as GPL. The GPL 2.0 remains in use on mt76x0, as well as two source files in mt7615 for which the license situation still needs to be clarified. Signed-off-by: Felix Fietkau <[email protected]>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/* Copyright (C) 2020 MediaTek Inc. */
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#ifndef __MT7921_REGS_H
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#define __MT7921_REGS_H
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#include "../mt792x_regs.h"
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#define MT_MDP_BASE 0x820cd000
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#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
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#define MT_MDP_DCR0 MT_MDP(0x000)
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#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
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#define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
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#define MT_MDP_DCR1 MT_MDP(0x004)
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#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
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#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
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#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
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#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
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#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
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#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
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#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
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#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
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#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
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#define MT_MDP_TO_HIF 0
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#define MT_MDP_TO_WM 1
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#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
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#define HOST_TX_DONE_INT_ENA8 BIT(12)
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#define HOST_TX_DONE_INT_ENA9 BIT(13)
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#define HOST_TX_DONE_INT_ENA10 BIT(14)
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#define HOST_TX_DONE_INT_ENA11 BIT(15)
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#define HOST_TX_DONE_INT_ENA12 BIT(16)
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#define HOST_TX_DONE_INT_ENA13 BIT(17)
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#define HOST_TX_DONE_INT_ENA14 BIT(18)
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#define HOST_RX_DONE_INT_ENA4 BIT(22)
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#define HOST_RX_DONE_INT_ENA5 BIT(23)
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#define HOST_TX_DONE_INT_ENA16 BIT(26)
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#define HOST_TX_DONE_INT_ENA17 BIT(27)
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/* WFDMA interrupt */
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#define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2
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#define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0
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#define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA4
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#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \
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MT_INT_RX_DONE_WM | \
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MT_INT_RX_DONE_WM2)
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#define MT_INT_TX_DONE_MCU_WM HOST_TX_DONE_INT_ENA17
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#define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16
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#define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0
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#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \
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MT_INT_TX_DONE_FWDL)
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#define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \
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MT_INT_TX_DONE_BAND0 | \
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GENMASK(18, 4))
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#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
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#define MT_INFRA_CFG_BASE 0xfe000
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#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
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#define MT_HIF_REMAP_L1 MT_INFRA(0x24c)
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#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
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#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
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#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
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#define MT_HIF_REMAP_BASE_L1 0x40000
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#define MT_WFSYS_SW_RST_B 0x18000140
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#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x200)
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#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
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#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x230)
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#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
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#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
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#endif
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