mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Deren WuandFelix Fietkau
2afc7285f7
Add mt7925, a new mac80211 driver for the MediaTek Wi-Fi 7 (802.11be) device Filogic 360, which can support Station, AP, P2P, and monitor modes. Filogic 360 supports max 4096-QAM/160MHz radio operation at 6 GHz, 5 GHz, or 2.4 GHz with 2x2 antennas. This chip supports PCIe and USB bus type. mt7925 supports Wi-Fi 6E and EHT rate with single link only at this moment, whereas Wi-Fi 7 and its specific features are working in progress. They will be introduced in further patches. The driver is build tested by Intel's kernel test robot with both GCC and Clang with several architecture. Sparse reports no warnings. There are multiple authors, they are listed in alphabetical order below. Co-developed-by: Hao Zhang <[email protected]> Signed-off-by: Hao Zhang <[email protected]> Co-developed-by: Leon Yen <[email protected]> Signed-off-by: Leon Yen <[email protected]> Co-developed-by: Lorenzo Bianconi <[email protected]> Signed-off-by: Lorenzo Bianconi <[email protected]> Co-developed-by: Mingyen Hsieh <[email protected]> Signed-off-by: Mingyen Hsieh <[email protected]> Co-developed-by: Nelson Yu <[email protected]> Signed-off-by: Nelson Yu <[email protected]> Co-developed-by: Quan Zhou <[email protected]> Signed-off-by: Quan Zhou <[email protected]> Co-developed-by: Rong Yan <[email protected]> Signed-off-by: Rong Yan <[email protected]> Signed-off-by: Deren Wu <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/* SPDX-License-Identifier: ISC */
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/* Copyright (C) 2023 MediaTek Inc. */
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#ifndef __MT7925_REGS_H
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#define __MT7925_REGS_H
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#include "../mt792x_regs.h"
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#define MT_MDP_BASE 0x820cc800
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#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
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#define MT_MDP_DCR0 MT_MDP(0x000)
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#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
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#define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
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#define MT_MDP_DCR1 MT_MDP(0x004)
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#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
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#define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8))
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#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
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#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
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#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
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#define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8))
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#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
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#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
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#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
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#define MT_MDP_TO_HIF 0
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#define MT_MDP_TO_WM 1
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#define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x228)
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#define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
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#define HOST_RX_DONE_INT_ENA4 BIT(12)
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#define HOST_RX_DONE_INT_ENA5 BIT(13)
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#define HOST_RX_DONE_INT_ENA6 BIT(14)
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#define HOST_RX_DONE_INT_ENA7 BIT(15)
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#define HOST_RX_DONE_INT_ENA8 BIT(16)
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#define HOST_RX_DONE_INT_ENA9 BIT(17)
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#define HOST_RX_DONE_INT_ENA10 BIT(18)
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#define HOST_RX_DONE_INT_ENA11 BIT(19)
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#define HOST_TX_DONE_INT_ENA15 BIT(25)
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#define HOST_TX_DONE_INT_ENA16 BIT(26)
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#define HOST_TX_DONE_INT_ENA17 BIT(27)
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/* WFDMA interrupt */
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#define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2
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#define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0
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#define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA1
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#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \
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MT_INT_RX_DONE_WM | \
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MT_INT_RX_DONE_WM2)
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#define MT_INT_TX_DONE_MCU_WM (HOST_TX_DONE_INT_ENA15 | \
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HOST_TX_DONE_INT_ENA17)
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#define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16
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#define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0
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#define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \
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MT_INT_TX_DONE_FWDL)
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#define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \
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MT_INT_TX_DONE_BAND0 | \
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GENMASK(18, 4))
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#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
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#define MT_INFRA_CFG_BASE 0xd1000
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#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
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#define MT_HIF_REMAP_L1 0x155024
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#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)
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#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
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#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
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#define MT_HIF_REMAP_BASE_L1 0x130000
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#define MT_HIF_REMAP_L2 0x0120
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#if IS_ENABLED(CONFIG_MT76_DEV)
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#define MT_HIF_REMAP_BASE_L2 (0x7c500000 - (0x7c000000 - 0x18000000))
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#else
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#define MT_HIF_REMAP_BASE_L2 0x18500000
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#endif
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#define MT_WFSYS_SW_RST_B 0x7c000140
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#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
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#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
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#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)
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#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
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#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14)
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#endif
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