mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Felix Fietkau
539b679660
Now that tx status reporting can figure out the first attempted rate, we can make switching from lower rates to higher rates more conservative. This reduces retries under bad link conditions and ensures that fallback rates get more test coverage Signed-off-by: Felix Fietkau <[email protected]>
597 lines
16 KiB
C
597 lines
16 KiB
C
/* SPDX-License-Identifier: ISC */
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#include <linux/etherdevice.h>
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#include "mt7603.h"
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#include "mac.h"
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#include "eeprom.h"
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const struct mt76_driver_ops mt7603_drv_ops = {
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.txwi_size = MT_TXD_SIZE,
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.tx_prepare_skb = mt7603_tx_prepare_skb,
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.tx_complete_skb = mt7603_tx_complete_skb,
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.rx_skb = mt7603_queue_rx_skb,
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.rx_poll_complete = mt7603_rx_poll_complete,
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.sta_ps = mt7603_sta_ps,
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.sta_add = mt7603_sta_add,
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.sta_assoc = mt7603_sta_assoc,
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.sta_remove = mt7603_sta_remove,
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.update_survey = mt7603_update_channel,
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};
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static void
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mt7603_set_tmac_template(struct mt7603_dev *dev)
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{
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u32 desc[5] = {
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[1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
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[3] = MT_TXD5_SW_POWER_MGMT
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};
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u32 addr;
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int i;
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addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
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addr += MT_CLIENT_TMAC_INFO_TEMPLATE;
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for (i = 0; i < ARRAY_SIZE(desc); i++)
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mt76_wr(dev, addr + 4 * i, desc[i]);
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}
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static void
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mt7603_dma_sched_init(struct mt7603_dev *dev)
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{
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int page_size = 128;
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int page_count;
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int max_len = 1792;
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int max_amsdu_pages = 4096 / page_size;
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int max_mcu_len = 4096;
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int max_beacon_len = 512 * 4 + max_len;
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int max_mcast_pages = 4 * max_len / page_size;
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int reserved_count = 0;
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int beacon_pages;
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int mcu_pages;
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int i;
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page_count = mt76_get_field(dev, MT_PSE_FC_P0,
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MT_PSE_FC_P0_MAX_QUOTA);
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beacon_pages = 4 * (max_beacon_len / page_size);
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mcu_pages = max_mcu_len / page_size;
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mt76_wr(dev, MT_PSE_FRP,
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FIELD_PREP(MT_PSE_FRP_P0, 7) |
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FIELD_PREP(MT_PSE_FRP_P1, 6) |
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FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));
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mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
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mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
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mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);
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mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);
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mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);
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mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));
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mt76_wr(dev, MT_SCH_2, max_amsdu_pages);
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for (i = 0; i <= 4; i++)
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mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages);
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reserved_count += 5 * max_amsdu_pages;
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mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);
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reserved_count += mcu_pages;
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mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);
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reserved_count += beacon_pages;
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mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages);
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reserved_count += max_mcast_pages;
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if (is_mt7603(dev))
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reserved_count = 0;
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mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count);
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if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) {
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mt76_wr(dev, MT_GROUP_THRESH(0),
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page_count - beacon_pages - mcu_pages);
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mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);
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mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);
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mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);
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mt76_wr(dev, MT_BMAP_1, 0x00000020);
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} else {
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mt76_wr(dev, MT_GROUP_THRESH(0), page_count);
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mt76_wr(dev, MT_BMAP_0, 0xffff);
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}
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mt76_wr(dev, MT_SCH_4, 0);
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for (i = 0; i <= 15; i++)
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mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);
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mt76_set(dev, MT_SCH_4, BIT(6));
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}
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static void
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mt7603_phy_init(struct mt7603_dev *dev)
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{
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int rx_chains = dev->mt76.antenna_mask;
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int tx_chains = hweight8(rx_chains) - 1;
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mt76_rmw(dev, MT_WF_RMAC_RMCR,
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(MT_WF_RMAC_RMCR_SMPS_MODE |
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MT_WF_RMAC_RMCR_RX_STREAMS),
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(FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
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FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
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mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
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tx_chains);
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dev->agc0 = mt76_rr(dev, MT_AGC(0));
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dev->agc3 = mt76_rr(dev, MT_AGC(3));
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}
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static void
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mt7603_mac_init(struct mt7603_dev *dev)
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{
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u8 bc_addr[ETH_ALEN];
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u32 addr;
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int i;
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mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0,
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(MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
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mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1,
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(MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
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(MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
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mt76_wr(dev, MT_AGG_LIMIT,
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FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
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mt76_wr(dev, MT_AGG_LIMIT_1,
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FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
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FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
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mt76_wr(dev, MT_AGG_CONTROL,
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FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |
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FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
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MT_AGG_CONTROL_NO_BA_AR_RULE);
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mt76_wr(dev, MT_AGG_RETRY_CONTROL,
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FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
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FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
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mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |
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FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096));
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mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
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mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
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mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31));
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mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT);
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mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
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mt76_wr(dev, MT_WF_RFCR1, 0);
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mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE);
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mt7603_set_tmac_template(dev);
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/* Enable RX group to HIF */
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addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
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mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS);
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/* Enable RX group to MCU */
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mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
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mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3);
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mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN);
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/* include preamble detection in CCA trigger signal */
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mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2);
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mt76_wr(dev, MT_RXREQ, 4);
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/* Configure all rx packets to HIF */
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mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);
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/* Configure MCU txs selection with aggregation */
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mt76_wr(dev, MT_DMA_TCFR0,
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FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
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MT_DMA_TCFR_TXS_AGGR_COUNT);
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/* Configure HIF txs selection with aggregation */
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mt76_wr(dev, MT_DMA_TCFR1,
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FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
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MT_DMA_TCFR_TXS_AGGR_COUNT | /* Maximum count */
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MT_DMA_TCFR_TXS_BIT_MAP);
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mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);
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for (i = 0; i < MT7603_WTBL_SIZE; i++)
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mt7603_wtbl_clear(dev, i);
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eth_broadcast_addr(bc_addr);
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mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr);
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dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED;
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rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED],
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&dev->global_sta.wcid);
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mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
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mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
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mt76_wr(dev, MT_AGG_ARUCR,
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
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mt76_wr(dev, MT_AGG_ARDCR,
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
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mt76_wr(dev, MT_AGG_ARCR,
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(MT_AGG_ARCR_INIT_RATE1 |
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FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
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MT_AGG_ARCR_RATE_DOWN_RATIO_EN |
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FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |
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FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));
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mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);
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mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER);
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mt76_clear(dev, MT_SEC_SCR, BIT(18));
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/* Set secondary beacon time offsets */
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for (i = 0; i <= 4; i++)
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mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET,
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(i + 1) * (20 + 4096));
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}
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static int
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mt7603_init_hardware(struct mt7603_dev *dev)
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{
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int i, ret;
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mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
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ret = mt7603_eeprom_init(dev);
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if (ret < 0)
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return ret;
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ret = mt7603_dma_init(dev);
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if (ret)
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return ret;
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mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
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mt7603_mac_dma_start(dev);
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dev->rxfilter = mt76_rr(dev, MT_WF_RFCR);
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set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
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for (i = 0; i < MT7603_WTBL_SIZE; i++) {
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mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE |
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FIELD_PREP(MT_PSE_RTA_TAG_ID, i));
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mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
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}
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ret = mt7603_mcu_init(dev);
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if (ret)
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return ret;
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mt7603_dma_sched_init(dev);
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mt7603_mcu_set_eeprom(dev);
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mt7603_phy_init(dev);
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mt7603_mac_init(dev);
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return 0;
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}
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#define CCK_RATE(_idx, _rate) { \
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.bitrate = _rate, \
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.flags = IEEE80211_RATE_SHORT_PREAMBLE, \
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.hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
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.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
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}
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#define OFDM_RATE(_idx, _rate) { \
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.bitrate = _rate, \
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.hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
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.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
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}
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static struct ieee80211_rate mt7603_rates[] = {
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CCK_RATE(0, 10),
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CCK_RATE(1, 20),
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CCK_RATE(2, 55),
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CCK_RATE(3, 110),
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OFDM_RATE(11, 60),
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OFDM_RATE(15, 90),
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OFDM_RATE(10, 120),
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OFDM_RATE(14, 180),
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OFDM_RATE(9, 240),
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OFDM_RATE(13, 360),
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OFDM_RATE(8, 480),
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OFDM_RATE(12, 540),
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};
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static const struct ieee80211_iface_limit if_limits[] = {
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{
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.max = 1,
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.types = BIT(NL80211_IFTYPE_ADHOC)
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}, {
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.max = MT7603_MAX_INTERFACES,
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.types = BIT(NL80211_IFTYPE_STATION) |
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#ifdef CONFIG_MAC80211_MESH
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BIT(NL80211_IFTYPE_MESH_POINT) |
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#endif
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BIT(NL80211_IFTYPE_AP)
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},
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};
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static const struct ieee80211_iface_combination if_comb[] = {
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{
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.limits = if_limits,
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.n_limits = ARRAY_SIZE(if_limits),
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.max_interfaces = 4,
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.num_different_channels = 1,
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.beacon_int_infra_match = true,
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}
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};
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static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on,
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u8 delay_off)
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{
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struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev,
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mt76);
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u32 val, addr;
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val = MT_LED_STATUS_DURATION(0xffff) |
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MT_LED_STATUS_OFF(delay_off) |
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MT_LED_STATUS_ON(delay_on);
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addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin));
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mt76_wr(dev, addr, val);
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addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin));
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mt76_wr(dev, addr, val);
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val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
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MT_LED_CTRL_KICK(mt76->led_pin);
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if (mt76->led_al)
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val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
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addr = mt7603_reg_map(dev, MT_LED_CTRL);
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mt76_wr(dev, addr, val);
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}
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static int mt7603_led_set_blink(struct led_classdev *led_cdev,
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unsigned long *delay_on,
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unsigned long *delay_off)
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{
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struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
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led_cdev);
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u8 delta_on, delta_off;
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delta_off = max_t(u8, *delay_off / 10, 1);
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delta_on = max_t(u8, *delay_on / 10, 1);
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mt7603_led_set_config(mt76, delta_on, delta_off);
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return 0;
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}
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static void mt7603_led_set_brightness(struct led_classdev *led_cdev,
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enum led_brightness brightness)
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{
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struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
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led_cdev);
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if (!brightness)
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mt7603_led_set_config(mt76, 0, 0xff);
|
|
else
|
|
mt7603_led_set_config(mt76, 0xff, 0);
|
|
}
|
|
|
|
static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr)
|
|
{
|
|
if (addr < 0x100000)
|
|
return addr;
|
|
|
|
return mt7603_reg_map(dev, addr);
|
|
}
|
|
|
|
static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset)
|
|
{
|
|
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
|
|
u32 addr = __mt7603_reg_addr(dev, offset);
|
|
|
|
return dev->bus_ops->rr(mdev, addr);
|
|
}
|
|
|
|
static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val)
|
|
{
|
|
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
|
|
u32 addr = __mt7603_reg_addr(dev, offset);
|
|
|
|
dev->bus_ops->wr(mdev, addr, val);
|
|
}
|
|
|
|
static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
|
|
{
|
|
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
|
|
u32 addr = __mt7603_reg_addr(dev, offset);
|
|
|
|
return dev->bus_ops->rmw(mdev, addr, mask, val);
|
|
}
|
|
|
|
static void
|
|
mt7603_regd_notifier(struct wiphy *wiphy,
|
|
struct regulatory_request *request)
|
|
{
|
|
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
|
|
struct mt7603_dev *dev = hw->priv;
|
|
|
|
dev->region = request->dfs_region;
|
|
dev->ed_monitor = dev->ed_monitor_enabled &&
|
|
dev->region == NL80211_DFS_ETSI;
|
|
}
|
|
|
|
static int
|
|
mt7603_txpower_signed(int val)
|
|
{
|
|
bool sign = val & BIT(6);
|
|
|
|
if (!(val & BIT(7)))
|
|
return 0;
|
|
|
|
val &= GENMASK(5, 0);
|
|
if (!sign)
|
|
val = -val;
|
|
|
|
return val;
|
|
}
|
|
|
|
static void
|
|
mt7603_init_txpower(struct mt7603_dev *dev,
|
|
struct ieee80211_supported_band *sband)
|
|
{
|
|
struct ieee80211_channel *chan;
|
|
u8 *eeprom = (u8 *)dev->mt76.eeprom.data;
|
|
int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7);
|
|
u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK];
|
|
bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1);
|
|
int max_offset, cur_offset;
|
|
int i;
|
|
|
|
if (ext_pa)
|
|
target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7);
|
|
|
|
if (target_power & BIT(6))
|
|
target_power = -(target_power & GENMASK(5, 0));
|
|
|
|
max_offset = 0;
|
|
for (i = 0; i < 14; i++) {
|
|
cur_offset = mt7603_txpower_signed(rate_power[i]);
|
|
max_offset = max(max_offset, cur_offset);
|
|
}
|
|
|
|
target_power += max_offset;
|
|
|
|
dev->tx_power_limit = target_power;
|
|
dev->mt76.txpower_cur = target_power;
|
|
|
|
target_power = DIV_ROUND_UP(target_power, 2);
|
|
|
|
/* add 3 dBm for 2SS devices (combined output) */
|
|
if (dev->mt76.antenna_mask & BIT(1))
|
|
target_power += 3;
|
|
|
|
for (i = 0; i < sband->n_channels; i++) {
|
|
chan = &sband->channels[i];
|
|
chan->max_power = min_t(int, chan->max_reg_power, target_power);
|
|
chan->orig_mpwr = target_power;
|
|
}
|
|
}
|
|
|
|
|
|
int mt7603_register_device(struct mt7603_dev *dev)
|
|
{
|
|
struct mt76_bus_ops *bus_ops;
|
|
struct ieee80211_hw *hw = mt76_hw(dev);
|
|
struct wiphy *wiphy = hw->wiphy;
|
|
int ret;
|
|
|
|
dev->bus_ops = dev->mt76.bus;
|
|
bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
|
|
GFP_KERNEL);
|
|
if (!bus_ops)
|
|
return -ENOMEM;
|
|
|
|
bus_ops->rr = mt7603_rr;
|
|
bus_ops->wr = mt7603_wr;
|
|
bus_ops->rmw = mt7603_rmw;
|
|
dev->mt76.bus = bus_ops;
|
|
|
|
spin_lock_init(&dev->ps_lock);
|
|
|
|
INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7603_mac_work);
|
|
tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet,
|
|
(unsigned long)dev);
|
|
|
|
/* Check for 7688, which only has 1SS */
|
|
dev->mt76.antenna_mask = 3;
|
|
if (mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4))
|
|
dev->mt76.antenna_mask = 1;
|
|
|
|
dev->slottime = 9;
|
|
|
|
ret = mt7603_init_hardware(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hw->queues = 4;
|
|
hw->max_rates = 3;
|
|
hw->max_report_rates = 7;
|
|
hw->max_rate_tries = 11;
|
|
|
|
hw->sta_data_size = sizeof(struct mt7603_sta);
|
|
hw->vif_data_size = sizeof(struct mt7603_vif);
|
|
|
|
wiphy->iface_combinations = if_comb;
|
|
wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
|
|
|
|
ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);
|
|
ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
|
|
|
|
/* init led callbacks */
|
|
if (IS_ENABLED(CONFIG_MT76_LEDS)) {
|
|
dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness;
|
|
dev->mt76.led_cdev.blink_set = mt7603_led_set_blink;
|
|
}
|
|
|
|
wiphy->interface_modes =
|
|
BIT(NL80211_IFTYPE_STATION) |
|
|
BIT(NL80211_IFTYPE_AP) |
|
|
#ifdef CONFIG_MAC80211_MESH
|
|
BIT(NL80211_IFTYPE_MESH_POINT) |
|
|
#endif
|
|
BIT(NL80211_IFTYPE_ADHOC);
|
|
|
|
wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
|
|
|
|
wiphy->reg_notifier = mt7603_regd_notifier;
|
|
|
|
ret = mt76_register_device(&dev->mt76, true, mt7603_rates,
|
|
ARRAY_SIZE(mt7603_rates));
|
|
if (ret)
|
|
return ret;
|
|
|
|
mt7603_init_debugfs(dev);
|
|
mt7603_init_txpower(dev, &dev->mt76.sband_2g.sband);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mt7603_unregister_device(struct mt7603_dev *dev)
|
|
{
|
|
tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
|
|
mt76_unregister_device(&dev->mt76);
|
|
mt7603_mcu_exit(dev);
|
|
mt7603_dma_cleanup(dev);
|
|
mt76_free_device(&dev->mt76);
|
|
}
|