mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
133 lines
2.8 KiB
C
133 lines
2.8 KiB
C
/*
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* Copyright (C) 2014 Felix Fietkau <[email protected]>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include "mt76.h"
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#include "trace.h"
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bool mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout)
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{
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u32 cur;
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timeout /= 10;
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do {
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cur = mt76_rr(dev, offset) & mask;
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if (cur == val)
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return true;
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udelay(10);
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} while (timeout-- > 0);
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return false;
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}
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bool mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout)
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{
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u32 cur;
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timeout /= 10;
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do {
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cur = mt76_rr(dev, offset) & mask;
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if (cur == val)
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return true;
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msleep(10);
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} while (timeout-- > 0);
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return false;
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}
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void mt76_write_reg_pairs(struct mt76_dev *dev,
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const struct mt76_reg_pair *data, int len)
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{
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while (len > 0) {
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mt76_wr(dev, data->reg, data->value);
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len--;
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data++;
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}
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}
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void mt76_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev->irq_lock, flags);
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dev->irqmask &= ~clear;
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dev->irqmask |= set;
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mt76_wr(dev, MT_INT_MASK_CSR, dev->irqmask);
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spin_unlock_irqrestore(&dev->irq_lock, flags);
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}
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irqreturn_t mt76_irq_handler(int irq, void *dev_instance)
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{
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struct mt76_dev *dev = dev_instance;
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u32 intr;
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intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
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mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
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if (!test_bit(MT76_STATE_INITAILIZED, &dev->state))
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return IRQ_NONE;
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trace_dev_irq(dev, intr, dev->irqmask);
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intr &= dev->irqmask;
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if (intr & MT_INT_TX_DONE_ALL) {
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mt76_irq_disable(dev, MT_INT_TX_DONE_ALL);
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tasklet_schedule(&dev->tx_tasklet);
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}
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if (intr & MT_INT_RX_DONE(0)) {
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mt76_irq_disable(dev, MT_INT_RX_DONE(0));
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napi_schedule(&dev->napi);
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}
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if (intr & MT_INT_RX_DONE(1)) {
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mt76_irq_disable(dev, MT_INT_RX_DONE(1));
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tasklet_schedule(&dev->rx_tasklet);
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}
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if (intr & MT_INT_PRE_TBTT)
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tasklet_schedule(&dev->pre_tbtt_tasklet);
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/* send buffered multicast frames now */
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if (intr & MT_INT_TBTT)
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mt76_kick_queue(dev, &dev->q_tx[MT_TXQ_PSD]);
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if (intr & MT_INT_TX_STAT) {
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mt76_mac_poll_tx_status(dev, true);
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tasklet_schedule(&dev->tx_tasklet);
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}
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return IRQ_HANDLED;
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}
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int mt76_set_channel(struct mt76_dev *dev, struct cfg80211_chan_def *chandef)
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{
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int ret;
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tasklet_disable(&dev->pre_tbtt_tasklet);
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cancel_delayed_work_sync(&dev->cal_work);
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mt76_mac_stop(dev, true);
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ret = mt76_phy_set_channel(dev, chandef);
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mt76_mac_resume(dev);
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tasklet_enable(&dev->pre_tbtt_tasklet);
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return ret;
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}
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