mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
Lorenzo BianconiandFelix Fietkau
4a11cb67dc
Move tx_amsdu histogram stats in mib_stats structure since registers are clear-on-read Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
518 lines
13 KiB
C
518 lines
13 KiB
C
// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc. */
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#include "mt7915.h"
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#include "eeprom.h"
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#include "mcu.h"
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/** global debugfs **/
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struct hw_queue_map {
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const char *name;
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u8 index;
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u8 pid;
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u8 qid;
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};
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static int
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mt7915_implicit_txbf_set(void *data, u64 val)
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{
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struct mt7915_dev *dev = data;
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if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
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return -EBUSY;
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dev->ibf = !!val;
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return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
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}
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static int
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mt7915_implicit_txbf_get(void *data, u64 *val)
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{
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struct mt7915_dev *dev = data;
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*val = dev->ibf;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get,
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mt7915_implicit_txbf_set, "%lld\n");
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/* test knob of system layer 1/2 error recovery */
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static int mt7915_ser_trigger_set(void *data, u64 val)
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{
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enum {
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SER_SET_RECOVER_L1 = 1,
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SER_SET_RECOVER_L2,
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SER_ENABLE = 2,
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SER_RECOVER
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};
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struct mt7915_dev *dev = data;
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int ret = 0;
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switch (val) {
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case SER_SET_RECOVER_L1:
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case SER_SET_RECOVER_L2:
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ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), 0);
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if (ret)
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return ret;
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return mt7915_mcu_set_ser(dev, SER_RECOVER, val, 0);
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default:
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break;
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}
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return ret;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL,
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mt7915_ser_trigger_set, "%lld\n");
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static int
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mt7915_radar_trigger(void *data, u64 val)
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{
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struct mt7915_dev *dev = data;
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return mt7915_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 1, 0, 0);
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,
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mt7915_radar_trigger, "%lld\n");
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static int
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mt7915_fw_debug_set(void *data, u64 val)
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{
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struct mt7915_dev *dev = data;
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enum {
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DEBUG_TXCMD = 62,
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DEBUG_CMD_RPT_TX,
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DEBUG_CMD_RPT_TRIG,
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DEBUG_SPL,
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DEBUG_RPT_RX,
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} debug;
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dev->fw_debug = !!val;
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mt7915_mcu_fw_log_2_host(dev, dev->fw_debug ? 2 : 0);
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for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++)
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mt7915_mcu_fw_dbg_ctrl(dev, debug, dev->fw_debug);
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return 0;
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}
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static int
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mt7915_fw_debug_get(void *data, u64 *val)
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{
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struct mt7915_dev *dev = data;
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*val = dev->fw_debug;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug, mt7915_fw_debug_get,
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mt7915_fw_debug_set, "%lld\n");
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static void
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mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy,
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struct seq_file *file)
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{
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struct mt7915_dev *dev = phy->dev;
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bool ext_phy = phy != &dev->phy;
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int bound[15], range[4], i, n;
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/* Tx ampdu stat */
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for (i = 0; i < ARRAY_SIZE(range); i++)
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range[i] = mt76_rr(dev, MT_MIB_ARNG(ext_phy, i));
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for (i = 0; i < ARRAY_SIZE(bound); i++)
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bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1;
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seq_printf(file, "\nPhy %d\n", ext_phy);
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seq_printf(file, "Length: %8d | ", bound[0]);
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for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)
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seq_printf(file, "%3d -%3d | ",
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bound[i] + 1, bound[i + 1]);
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seq_puts(file, "\nCount: ");
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n = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
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for (i = 0; i < ARRAY_SIZE(bound); i++)
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seq_printf(file, "%8d | ", dev->mt76.aggr_stats[i + n]);
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seq_puts(file, "\n");
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seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);
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}
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static void
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mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s)
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{
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static const char * const bw[] = {
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"BW20", "BW40", "BW80", "BW160"
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};
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struct mib_stats *mib = &phy->mib;
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/* Tx Beamformer monitor */
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seq_puts(s, "\nTx Beamformer applied PPDU counts: ");
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seq_printf(s, "iBF: %d, eBF: %d\n",
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mib->tx_bf_ibf_ppdu_cnt,
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mib->tx_bf_ebf_ppdu_cnt);
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/* Tx Beamformer Rx feedback monitor */
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seq_puts(s, "Tx Beamformer Rx feedback statistics: ");
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seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ",
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mib->tx_bf_rx_fb_all_cnt,
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mib->tx_bf_rx_fb_he_cnt,
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mib->tx_bf_rx_fb_vht_cnt,
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mib->tx_bf_rx_fb_ht_cnt);
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seq_printf(s, "%s, NC: %d, NR: %d\n",
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bw[mib->tx_bf_rx_fb_bw],
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mib->tx_bf_rx_fb_nc_cnt,
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mib->tx_bf_rx_fb_nr_cnt);
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/* Tx Beamformee Rx NDPA & Tx feedback report */
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seq_printf(s, "Tx Beamformee successful feedback frames: %d\n",
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mib->tx_bf_fb_cpl_cnt);
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seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n",
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mib->tx_bf_fb_trig_cnt);
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/* Tx SU & MU counters */
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seq_printf(s, "Tx multi-user Beamforming counts: %d\n",
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mib->tx_bf_cnt);
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seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt);
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seq_printf(s, "Tx multi-user successful MPDU counts: %d\n",
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mib->tx_mu_acked_mpdu_cnt);
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seq_printf(s, "Tx single-user successful MPDU counts: %d\n",
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mib->tx_su_acked_mpdu_cnt);
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seq_puts(s, "\n");
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}
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static int
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mt7915_tx_stats_show(struct seq_file *file, void *data)
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{
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struct mt7915_phy *phy = file->private;
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struct mt7915_dev *dev = phy->dev;
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struct mib_stats *mib = &phy->mib;
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int i;
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mutex_lock(&dev->mt76.mutex);
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mt7915_ampdu_stat_read_phy(phy, file);
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mt7915_mac_update_stats(phy);
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mt7915_txbf_stat_read_phy(phy, file);
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/* Tx amsdu info */
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seq_puts(file, "Tx MSDU statistics:\n");
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for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
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seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",
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i + 1, mib->tx_amsdu[i]);
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if (mib->tx_amsdu_cnt)
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seq_printf(file, "(%3d%%)\n",
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mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt);
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else
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seq_puts(file, "\n");
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}
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mutex_unlock(&dev->mt76.mutex);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
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static void
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mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
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const struct hw_queue_map *map)
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{
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struct mt7915_phy *phy = s->private;
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struct mt7915_dev *dev = phy->dev;
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u32 i, val;
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val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
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for (i = 0; i < size; i++) {
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u32 ctrl, head, tail, queued;
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if (val & BIT(map[i].index))
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continue;
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ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
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mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
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head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
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GENMASK(11, 0));
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tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
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GENMASK(27, 16));
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queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
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GENMASK(11, 0));
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seq_printf(s, "\t%s: ", map[i].name);
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seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",
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queued, head, tail);
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}
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}
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static void
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mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
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{
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struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
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struct mt7915_dev *dev = msta->vif->phy->dev;
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struct seq_file *s = data;
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u8 ac;
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for (ac = 0; ac < 4; ac++) {
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u32 qlen, ctrl, val;
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u32 idx = msta->wcid.idx >> 5;
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u8 offs = msta->wcid.idx & GENMASK(4, 0);
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ctrl = BIT(31) | BIT(11) | (ac << 24);
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val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
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if (val & BIT(offs))
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continue;
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mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
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qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
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GENMASK(11, 0));
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seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
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sta->addr, msta->wcid.idx, msta->vif->wmm_idx,
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ac, qlen);
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}
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}
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static int
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mt7915_hw_queues_show(struct seq_file *file, void *data)
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{
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struct mt7915_phy *phy = file->private;
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struct mt7915_dev *dev = phy->dev;
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static const struct hw_queue_map ple_queue_map[] = {
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{ "CPU_Q0", 0, 1, MT_CTX0 },
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{ "CPU_Q1", 1, 1, MT_CTX0 + 1 },
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{ "CPU_Q2", 2, 1, MT_CTX0 + 2 },
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{ "CPU_Q3", 3, 1, MT_CTX0 + 3 },
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{ "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },
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{ "BMC_Q0", 9, 2, MT_LMAC_BMC0 },
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{ "BCN_Q0", 10, 2, MT_LMAC_BCN0 },
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{ "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 },
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{ "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 },
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{ "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 },
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{ "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 },
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{ "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 },
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};
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static const struct hw_queue_map pse_queue_map[] = {
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{ "CPU Q0", 0, 1, MT_CTX0 },
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{ "CPU Q1", 1, 1, MT_CTX0 + 1 },
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{ "CPU Q2", 2, 1, MT_CTX0 + 2 },
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{ "CPU Q3", 3, 1, MT_CTX0 + 3 },
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{ "HIF_Q0", 8, 0, MT_HIF0 },
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{ "HIF_Q1", 9, 0, MT_HIF0 + 1 },
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{ "HIF_Q2", 10, 0, MT_HIF0 + 2 },
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{ "HIF_Q3", 11, 0, MT_HIF0 + 3 },
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{ "HIF_Q4", 12, 0, MT_HIF0 + 4 },
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{ "HIF_Q5", 13, 0, MT_HIF0 + 5 },
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{ "LMAC_Q", 16, 2, 0 },
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{ "MDP_TXQ", 17, 2, 1 },
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{ "MDP_RXQ", 18, 2, 2 },
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{ "SEC_TXQ", 19, 2, 3 },
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{ "SEC_RXQ", 20, 2, 4 },
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};
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u32 val, head, tail;
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/* ple queue */
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val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
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head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
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tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
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seq_puts(file, "PLE page info:\n");
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seq_printf(file,
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"\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",
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val, head, tail);
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val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
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head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
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tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
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seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",
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val, head, tail);
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seq_puts(file, "PLE non-empty queue info:\n");
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mt7915_hw_queue_read(file, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
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&ple_queue_map[0]);
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/* iterate per-sta ple queue */
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ieee80211_iterate_stations_atomic(phy->mt76->hw,
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mt7915_sta_hw_queue_read, file);
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/* pse queue */
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seq_puts(file, "PSE non-empty queue info:\n");
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mt7915_hw_queue_read(file, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
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&pse_queue_map[0]);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues);
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static int
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mt7915_xmit_queues_show(struct seq_file *file, void *data)
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{
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struct mt7915_phy *phy = file->private;
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struct mt7915_dev *dev = phy->dev;
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struct {
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struct mt76_queue *q;
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char *queue;
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} queue_map[] = {
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{ phy->mt76->q_tx[MT_TXQ_BE], " MAIN" },
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{ dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },
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{ dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },
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{ dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },
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};
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int i;
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seq_puts(file, " queue | hw-queued | head | tail |\n");
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for (i = 0; i < ARRAY_SIZE(queue_map); i++) {
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struct mt76_queue *q = queue_map[i].q;
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if (!q)
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continue;
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seq_printf(file, " %s | %9d | %9d | %9d |\n",
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queue_map[i].queue, q->queued, q->head,
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q->tail);
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues);
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static int
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mt7915_rate_txpower_show(struct seq_file *file, void *data)
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{
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static const char * const sku_group_name[] = {
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"CCK", "OFDM", "HT20", "HT40",
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"VHT20", "VHT40", "VHT80", "VHT160",
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"RU26", "RU52", "RU106", "RU242/SU20",
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"RU484/SU40", "RU996/SU80", "RU2x996/SU160"
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};
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struct mt7915_phy *phy = file->private;
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s8 txpower[MT7915_SKU_RATE_NUM], *buf;
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int i;
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seq_printf(file, "\nBand %d\n", phy != &phy->dev->phy);
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mt7915_mcu_get_txpower_sku(phy, txpower, sizeof(txpower));
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for (i = 0, buf = txpower; i < ARRAY_SIZE(mt7915_sku_group_len); i++) {
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u8 mcs_num = mt7915_sku_group_len[i];
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if (i >= SKU_VHT_BW20 && i <= SKU_VHT_BW160)
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mcs_num = 10;
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mt76_seq_puts_array(file, sku_group_name[i], buf, mcs_num);
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buf += mt7915_sku_group_len[i];
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(mt7915_rate_txpower);
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static int
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mt7915_twt_stats(struct seq_file *s, void *data)
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{
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struct mt7915_dev *dev = dev_get_drvdata(s->private);
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struct mt7915_twt_flow *iter;
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rcu_read_lock();
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seq_puts(s, " wcid | id | flags | exp | mantissa");
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seq_puts(s, " | duration | tsf |\n");
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list_for_each_entry_rcu(iter, &dev->twt_list, list)
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seq_printf(s,
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"%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",
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iter->wcid, iter->id,
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iter->sched ? 's' : 'u',
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iter->protection ? 'p' : '-',
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iter->trigger ? 't' : '-',
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iter->flowtype ? '-' : 'a',
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iter->exp, iter->mantissa,
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iter->duration, iter->tsf);
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rcu_read_unlock();
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return 0;
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}
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|
|
int mt7915_init_debugfs(struct mt7915_phy *phy)
|
|
{
|
|
struct mt7915_dev *dev = phy->dev;
|
|
bool ext_phy = phy != &dev->phy;
|
|
struct dentry *dir;
|
|
|
|
dir = mt76_register_debugfs_fops(phy->mt76, NULL);
|
|
if (!dir)
|
|
return -ENOMEM;
|
|
|
|
debugfs_create_file("hw-queues", 0400, dir, phy,
|
|
&mt7915_hw_queues_fops);
|
|
debugfs_create_file("xmit-queues", 0400, dir, phy,
|
|
&mt7915_xmit_queues_fops);
|
|
debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops);
|
|
debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
|
|
debugfs_create_file("implicit_txbf", 0600, dir, dev,
|
|
&fops_implicit_txbf);
|
|
debugfs_create_file("txpower_sku", 0400, dir, phy,
|
|
&mt7915_rate_txpower_fops);
|
|
debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
|
|
mt7915_twt_stats);
|
|
debugfs_create_file("ser_trigger", 0200, dir, dev, &fops_ser_trigger);
|
|
if (!dev->dbdc_support || ext_phy) {
|
|
debugfs_create_u32("dfs_hw_pattern", 0400, dir,
|
|
&dev->hw_pattern);
|
|
debugfs_create_file("radar_trigger", 0200, dir, dev,
|
|
&fops_radar_trigger);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MAC80211_DEBUGFS
|
|
/** per-station debugfs **/
|
|
|
|
static int mt7915_sta_fixed_rate_set(void *data, u64 rate)
|
|
{
|
|
struct ieee80211_sta *sta = data;
|
|
struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
|
|
|
|
/* usage: <he ltf> <tx mode> <ldpc> <stbc> <bw> <gi> <nss> <mcs>
|
|
* <tx mode>: see enum mt76_phy_type
|
|
*/
|
|
return mt7915_mcu_set_fixed_rate(msta->vif->phy->dev, sta, rate);
|
|
}
|
|
|
|
DEFINE_DEBUGFS_ATTRIBUTE(fops_fixed_rate, NULL,
|
|
mt7915_sta_fixed_rate_set, "%llx\n");
|
|
|
|
static int
|
|
mt7915_queues_show(struct seq_file *s, void *data)
|
|
{
|
|
struct ieee80211_sta *sta = s->private;
|
|
|
|
mt7915_sta_hw_queue_read(s, sta);
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(mt7915_queues);
|
|
|
|
void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
|
struct ieee80211_sta *sta, struct dentry *dir)
|
|
{
|
|
debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);
|
|
debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops);
|
|
}
|
|
|
|
#endif
|