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ED/CCA needs to be disable before stopping the MAC to avoid hangs from tx being blocked. It must only be enabled again after the MAC has been started again. In many places this wasn't done properly, so fix this by always clearing the relevant ED/CCA bits in mt76x2_mac_stop and set it up again after channel change or calibration is done Signed-off-by: Felix Fietkau <[email protected]>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
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* Copyright (C) 2016 Felix Fietkau <[email protected]>
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* Copyright (C) 2018 Lorenzo Bianconi <[email protected]>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "mt76x2.h"
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void mt76x2_mac_stop(struct mt76x02_dev *dev, bool force)
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{
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bool stopped = false;
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u32 rts_cfg;
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int i;
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mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
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mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN);
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mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
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rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
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mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
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/* Wait for MAC to become idle */
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for (i = 0; i < 300; i++) {
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if ((mt76_rr(dev, MT_MAC_STATUS) &
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(MT_MAC_STATUS_RX | MT_MAC_STATUS_TX)) ||
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mt76_rr(dev, MT_BBP(IBI, 12))) {
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udelay(1);
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continue;
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}
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stopped = true;
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break;
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}
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if (force && !stopped) {
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mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
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mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
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mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
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mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
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}
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mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
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}
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EXPORT_SYMBOL_GPL(mt76x2_mac_stop);
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