mirror of
https://github.com/outbackdingo/mt76.git
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Thomas GleixnerandFelix Fietkau
5dc6f6fcc0
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Richard Fontana <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* (c) Copyright 2002-2010, Ralink Technology, Inc.
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* Copyright (C) 2018 Stanislaw Gruszka <[email protected]>
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*/
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#ifndef _MT76X0_PHY_H_
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#define _MT76X0_PHY_H_
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#define RF_G_BAND 0x0100
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#define RF_A_BAND 0x0200
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#define RF_A_BAND_LB 0x0400
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#define RF_A_BAND_MB 0x0800
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#define RF_A_BAND_HB 0x1000
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#define RF_A_BAND_11J 0x2000
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#define RF_BW_20 1
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#define RF_BW_40 2
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#define RF_BW_10 4
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#define RF_BW_80 8
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#define MT_RF(bank, reg) ((bank) << 16 | (reg))
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#define MT_RF_BANK(offset) ((offset) >> 16)
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#define MT_RF_REG(offset) ((offset) & 0xff)
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#define MT_RF_VCO_BP_CLOSE_LOOP BIT(3)
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#define MT_RF_VCO_BP_CLOSE_LOOP_MASK GENMASK(3, 0)
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#define MT_RF_VCO_CAL_MASK GENMASK(2, 0)
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#define MT_RF_START_TIME 0x3
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#define MT_RF_START_TIME_MASK GENMASK(2, 0)
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#define MT_RF_SETTLE_TIME_MASK GENMASK(6, 4)
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#define MT_RF_PLL_DEN_MASK GENMASK(4, 0)
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#define MT_RF_PLL_K_MASK GENMASK(4, 0)
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#define MT_RF_SDM_RESET_MASK BIT(7)
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#define MT_RF_SDM_MASH_PRBS_MASK GENMASK(6, 2)
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#define MT_RF_SDM_BP_MASK BIT(1)
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#define MT_RF_ISI_ISO_MASK GENMASK(7, 6)
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#define MT_RF_PFD_DLY_MASK GENMASK(5, 4)
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#define MT_RF_CLK_SEL_MASK GENMASK(3, 2)
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#define MT_RF_XO_DIV_MASK GENMASK(1, 0)
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struct mt76x0_bbp_switch_item {
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u16 bw_band;
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struct mt76_reg_pair reg_pair;
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};
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struct mt76x0_rf_switch_item {
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u32 rf_bank_reg;
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u16 bw_band;
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u8 value;
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};
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struct mt76x0_freq_item {
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u8 channel;
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u32 band;
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u8 pllR37;
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u8 pllR36;
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u8 pllR35;
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u8 pllR34;
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u8 pllR33;
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u8 pllR32_b7b5;
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u8 pllR32_b4b0; /* PLL_DEN (Denomina - 8) */
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u8 pllR31_b7b5;
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u8 pllR31_b4b0; /* PLL_K (Nominator *)*/
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u8 pllR30_b7; /* sdm_reset_n */
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u8 pllR30_b6b2; /* sdmmash_prbs,sin */
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u8 pllR30_b1; /* sdm_bp */
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u16 pll_n; /* R30<0>, R29<7:0> (hex) */
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u8 pllR28_b7b6; /* isi,iso */
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u8 pllR28_b5b4; /* pfd_dly */
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u8 pllR28_b3b2; /* clksel option */
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u32 pll_sdm_k; /* R28<1:0>, R27<7:0>, R26<7:0> (hex) SDM_k */
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u8 pllR24_b1b0; /* xo_div */
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};
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struct mt76x0_rate_pwr_item {
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s8 mcs_power;
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u8 rf_pa_mode;
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};
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struct mt76x0_rate_pwr_tab {
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struct mt76x0_rate_pwr_item cck[4];
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struct mt76x0_rate_pwr_item ofdm[8];
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struct mt76x0_rate_pwr_item ht[8];
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struct mt76x0_rate_pwr_item vht[10];
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struct mt76x0_rate_pwr_item stbc[8];
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struct mt76x0_rate_pwr_item mcs32;
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};
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#endif /* _MT76X0_PHY_H_ */
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