/* * Copyright (C) 2015 Felix Fietkau * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 * as published by the Free Software Foundation * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __MT7603_REGS_H #define __MT7603_REGS_H #define MT_HW_REV 0x1000 #define MT_HW_CHIPID 0x1008 #define MT_TOP_MISC2 0x1134 #define MT_MCU_BASE 0x2000 #define MT_MCU(ofs) (MT_MCU_BASE + (ofs)) #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500) #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0) #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18) #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504) #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0) #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19) #define MT_HIF_BASE 0x4000 #define MT_HIF(ofs) (MT_HIF_BASE + (ofs)) #define MT_INT_SOURCE_CSR MT_HIF(0x200) #define MT_INT_MASK_CSR MT_HIF(0x204) #define MT_DELAY_INT_CFG MT_HIF(0x204) #define MT_INT_RX_DONE(_n) BIT(_n) #define MT_INT_RX_DONE_ALL GENMASK(1, 0) #define MT_INT_TX_DONE_ALL GENMASK(19, 4) #define MT_INT_TX_DONE(_n) BIT(_n + 4) #define MT_INT_RX_COHERENT BIT(20) #define MT_INT_TX_COHERENT BIT(21) #define MT_INT_PRE_TBTT BIT(27) #define MT_INT_MCU_CMD BIT(30) #define MT_WPDMA_GLO_CFG MT_HIF(0x208) #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) #define MT_WPDMA_RST_IDX MT_HIF(0x20c) #define MT_TX_RING_BASE MT_HIF(0x300) #define MT_RX_RING_BASE MT_HIF(0x400) #define MT_TXTIME_THRESH_BASE MT_HIF(0x500) #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4)) #define MT_PAGE_COUNT_BASE MT_HIF(0x540) #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4)) #define MT_SCH_1 MT_HIF(0x588) #define MT_SCH_2 MT_HIF(0x58c) #define MT_SCH_3 MT_HIF(0x590) #define MT_SCH_4 MT_HIF(0x594) #define MT_SCH_4_FORCE_QID GENMASK(4, 0) #define MT_SCH_4_BYPASS BIT(5) #define MT_GROUP_THRESH_BASE MT_HIF(0x598) #define MT_GROUP_THRESH(n) (MT_GROUP_THRESH_BASE + ((n) * 4)) #define MT_QUEUE_PRIORITY_1 MT_HIF(0x580) #define MT_QUEUE_PRIORITY_2 MT_HIF(0x584) #define MT_BMAP_0 MT_HIF(0x5b0) #define MT_BMAP_1 MT_HIF(0x5b4) #define MT_BMAP_2 MT_HIF(0x5b8) #define MT_HIGH_PRIORITY_1 MT_HIF(0x5bc) #define MT_HIGH_PRIORITY_2 MT_HIF(0x5c0) #define MT_PRIORITY_MASK MT_HIF(0x5c4) #define MT_RSV_MAX_THRESH MT_HIF(0x5c8) #define MT_PSE_BASE 0x8000 #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) #define MT_PSE_FC_P0 MT_PSE(0x120) #define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0) #define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16) #define MT_PSE_FRP MT_PSE(0x138) #define MT_PSE_FRP_P0 GENMASK(2, 0) #define MT_PSE_FRP_P1 GENMASK(5, 3) #define MT_PSE_FRP_P2_RQ0 GENMASK(8, 6) #define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9) #define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12) #define MT_WF_PHY_BASE 0x10000 #define MT_WF_PHY_OFFSET 0x1000 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) #define MT_WF_PHY_CR_RXTD_BASE MT_WF_PHY(0x65c) #define MT_WF_PHY_CR_RXTD(n) (MT_WF_PHY_CR_RXTD_BASE + ((n) * 4)) #define MT_WF_PHY_CR_TSSI_BASE MT_WF_PHY(0xd00) #define MT_WF_PHY_CR_TSSI(phy, n) (MT_WF_PHY_CR_TSSI_BASE + \ ((phy) * MT_WF_PHY_OFFSET) + \ ((n) * 4)) #define MT_WF_AGG_BASE 0x21200 #define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs)) #define MT_AGG_TMP MT_WF_AGG(0x0d8) #define MT_AGG_BWCR MT_WF_AGG(0x0ec) #define MT_AGG_BWCR_BW GENMASK(3, 2) #define MT_WF_DMA_BASE 0x21c00 #define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs)) #define MT_DMA_DCR0 MT_WF_DMA(0x000) #define MT_DMA_DCR1 MT_WF_DMA(0x004) #define MT_DMA_RCFR0 MT_WF_DMA(0x070) #define MT_DMA_VCFR0 MT_WF_DMA(0x07c) #define MT_DMA_TMCFR0 MT_WF_DMA(0x088) #define MT_WF_ARB_BASE 0x21400 #define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs)) #define MT_WF_ARB_RQCR MT_WF_ARB(0x070) #define MT_WF_ARB_RQCR_RX_START BIT(0) #define MT_WF_ARB_RQCR_RXV_START BIT(4) #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7) #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8) #define MT_WF_ARB_SCR MT_WF_ARB(0x080) #define MT_WF_ARB_TX_DISABLE BIT(8) #define MT_WF_ARB_RX_DISABLE BIT(9) #define MT_WF_ARB_TX_START_0 MT_WF_ARB(0x100) #define MT_WF_ARB_TX_START_1 MT_WF_ARB(0x104) #define MT_WF_ARB_TX_FLUSH_0 MT_WF_ARB(0x108) #define MT_WF_ARB_TX_FLUSH_1 MT_WF_ARB(0x10c) #define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110) #define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114) #define MT_WF_TMAC_BASE 0x21600 #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs)) #define MT_WF_TMAC_TCR MT_WF_TMAC(0x000) #define MT_WF_TMAC_TCR_BLINK_SEL GENMASK(7, 6) #define MT_WF_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8) #define MT_WF_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12) #define MT_WF_TMAC_TCR_RTS_SIGTA BIT(14) #define MT_WF_TMAC_TCR_LDPC_OFS BIT(15) #define MT_WF_TMAC_TCR_TX_STREAMS GENMASK(17, 16) #define MT_WF_TMAC_SCH_IDLE_SEL GENMASK(19, 18) #define MT_WF_TMAC_SCH_DET_PER_IOD BIT(20) #define MT_WF_TMAC_DCH_DET_DISABLE BIT(21) #define MT_WF_TMAC_TX_RIFS BIT(22) #define MT_WF_TMAC_RX_RIFS_MODE BIT(23) #define MT_WF_TMAC_TXOP_TBTT_CONTROL BIT(24) #define MT_WF_TMAC_TBTT_TX_STOP_CONTROL BIT(25) #define MT_WF_TMAC_TXOP_BURST_STOP BIT(26) #define MT_WF_TMAC_RDG_RA_MODE BIT(27) #define MT_WF_TMAC_RDG_RESP BIT(29) #define MT_WF_TMAC_RDG_GRANT_NO_PENDING BIT(30) #define MT_WF_TMAC_SMOOTHING BIT(31) #define MT_WF_RMAC_BASE 0x21800 #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs)) #define MT_WF_RFCR MT_WF_RMAC(0x000) #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) #define MT_WF_RFCR_DROP_VERSION BIT(3) #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) #define MT_WF_RFCR_DROP_MCAST BIT(5) #define MT_WF_RFCR_DROP_BCAST BIT(6) #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) #define MT_WF_RFCR_DROP_A3_MAC BIT(8) #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) #define MT_WF_RFCR_DROP_CTS BIT(14) #define MT_WF_RFCR_DROP_RTS BIT(15) #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) #define MT_WF_RFCR_DROP_NDPA BIT(20) #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) #define MT_WF_RMACDR MT_WF_RMAC(0x078) #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0) #define MT_WF_RMACDR_TSF_TIM BIT(4) #define MT_WF_RMACDR_MBSSID_MASK GENMASK(25, 24) #define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26) #define MT_WF_RMACDR_MAXLEN_20BIT BIT(30) #define MT_WF_RMAC_RMCR MT_WF_RMAC(0x080) #define MT_WF_RMAC_RMCR_SMPS_MODE GENMASK(21, 20) #define MT_WF_RMAC_RMCR_RX_STREAMS GENMASK(24, 22) #define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25) #define MT_WF_RMAC_CH_FREQ MT_WF_RMAC(0x090) #define MT_WF_RMAC_MAXMINLEN MT_WF_RMAC(0x098) #define MT_WF_RFCR1 MT_WF_RMAC(0x0a4) #define MT_WF_RMAC_TMR_PA MT_WF_RMAC(0x0e0) #define MT_WTBL_OFF_BASE 0x23000 #define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n)) #define MT_WTBL_UPDATE MT_WTBL_OFF(0x000) #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0) #define MT_WTBL_UPDATE_WTBL2 BIT(11) #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13) #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14) #define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15) #define MT_WTBL_UPDATE_BUSY BIT(16) #define MT_WTBL_RMVTCR MT_WTBL_OFF(0x008) #define MT_LPON_BASE 0x24000 #define MT_LPON(n) (MT_LPON_BASE + (n)) #define MT_LPON_BTEIR MT_LPON(0x020) #define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29) #define MT_WTBL1_BASE 0x28000 #define MT_PCIE_REMAP_BASE_1 0x40000 #define MT_PCIE_REMAP_BASE_2 0x80000 #define MT_TX_HW_QUEUE_MGMT 4 #define MT_TX_HW_QUEUE_MCU 5 #define MT_TX_HW_QUEUE_BCN 7 #define MT_TX_HW_QUEUE_BMC 8 #define MT_CLIENT_BASE_PHYS_ADDR 0x800c0000 #define MT_CLIENT_TMAC_INFO_TEMPLATE 0x040 #define MT_CLIENT_RXINF 0x068 #define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0) #define MT_PSE_BASE_PHYS_ADDR 0xa0000000 #define MT_PSE_WTBL_2_PHYS_ADDR 0xa5000000 #define MT_WTBL1_SIZE (8 * 4) #define MT_WTBL2_SIZE (16 * 4) #define MT_WTBL3_SIZE (16 * 4) #define MT_WTBL4_SIZE (8 * 4) #define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0) #define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16) #define MT_WTBL1_W0_RX_CHECK_A1 BIT(22) #define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23) #define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25) #define MT_WTBL1_W0_RX_KEY_VALID BIT(26) #define MT_WTBL1_W0_RX_IK_VALID BIT(27) #define MT_WTBL1_W0_RX_VALID BIT(28) #define MT_WTBL1_W0_RX_CHECK_A2 BIT(29) #define MT_WTBL1_W0_RX_DATA_VALID BIT(30) #define MT_WTBL1_W0_WRITE_BURST BIT(31) #define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0) #define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0) #define MT_WTBL1_W2_KEY_TYPE GENMASK(6, 3) #define MT_WTBL1_W2_EVEN_PN BIT(7) #define MT_WTBL1_W2_TO_DS BIT(8) #define MT_WTBL1_W2_FROM_DS BIT(9) #define MT_WTBL1_W2_HEADER_TRANS BIT(10) #define MT_WTBL1_W2_AMPDU_FACTOR GENMASK(13, 11) #define MT_WTBL1_W2_PWR_MGMT BIT(14) #define MT_WTBL1_W2_RDG BIT(15) #define MT_WTBL1_W2_RTS BIT(16) #define MT_WTBL1_W2_CFACK BIT(17) #define MT_WTBL1_W2_RDG_BA BIT(18) #define MT_WTBL1_W2_SMPS BIT(19) #define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20) #define MT_WTBL1_W2_DYN_BW BIT(21) #define MT_WTBL1_W2_LDPC BIT(22) #define MT_WTBL1_W2_ITXBF BIT(23) #define MT_WTBL1_W2_ETXBF BIT(24) #define MT_WTBL1_W2_TXOP_PS BIT(25) #define MT_WTBL1_W2_MESH BIT(26) #define MT_WTBL1_W2_QOS BIT(27) #define MT_WTBL1_W2_HT BIT(28) #define MT_WTBL1_W2_VHT BIT(29) #define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30) #define MT_WTBL1_W2_GROUP_ID BIT(31) #define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0) #define MT_WTBL1_W3_WTBL2_ENTRY_ID GENMASK(15, 11) #define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16) #define MT_WTBL1_W3_CHECK_PER BIT(27) #define MT_WTBL1_W3_UPDATE_I_PSM BIT(28) #define MT_WTBL1_W3_I_PSM BIT(29) #define MT_WTBL1_W3_POWER_SAVE BIT(30) #define MT_WTBL1_W3_SKIP_TX BIT(31) #define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0) #define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11) #define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17) #define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23) #define MT_WTBL2_W0_PN_LO GENMASK(31, 0) #define MT_WTBL2_W1_PN_HI GENMASK(15, 0) #define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16) #define MT_WTBL2_W2_TID0_SN GENMASK(11, 0) #define MT_WTBL2_W2_TID1_SN GENMASK(23, 12) #define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24) #define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0) #define MT_WTBL2_W3_TID3_SN GENMASK(15, 4) #define MT_WTBL2_W3_TID4_SN GENMASK(27, 16) #define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28) #define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0) #define MT_WTBL2_W4_TID6_SN GENMASK(19, 8) #define MT_WTBL2_W4_TID7_SN GENMASK(31, 20) #define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0) #define MT_WTBL2_W5_FAIL_COUNT_RATE1 GENAMSK(31, 16) #define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0) #define MT_WTBL2_W6_TX_COUNT_RATE3 GENMASK(15, 8) #define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16) #define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24) #define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0) #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16) #define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0) #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16) #define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0) #define MT_WTBL2_W9_SPATIAL_EXT BIT(5) #define MT_WTBL2_W9_ANT_PRIORITY GENMASK(8, 6) #define MT_WTBL2_W9_CC_BW_SEL GENMASK(10, 9) #define MT_WTBL2_W9_CHANGE_BW_RATE GENMASK(13, 11) #define MT_WTBL2_W9_BW_CAP GENMASK(15, 14) #define MT_WTBL2_W9_SHORT_GI_20 BIT(16) #define MT_WTBL2_W9_SHORT_GI_40 BIT(17) #define MT_WTBL2_W9_SHORT_GI_80 BIT(18) #define MT_WTBL2_W9_SHORT_GI_160 BIT(19) #define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23) #define MT_WTBL2_W9_MPDU_OK_COUNT GENMASK(28, 26) #define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29) #define MT_WTBL2_W10_RATE1 GENMASK(11, 0) #define MT_WTBL2_W10_RATE2 GENMASK(23, 12) #define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24) #define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0) #define MT_WTBL2_W11_RATE4 GENMASK(15, 4) #define MT_WTBL2_W11_RATE5 GENMASK(27, 16) #define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28) #define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0) #define MT_WTBL2_W12_RATE7 GENMASK(19, 8) #define MT_WTBL2_W12_RATE8 GENMASK(31, 20) #define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0) #define MT_WTBL2_W13_AVG_RCPI1 GENMASK(15, 8) #define MT_WTBL2_W13_AVG_RCPI2 GENAMSK(23, 16) #define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0) #define MT_WTBL2_W14_CC_NOISE_2S GENMASK(13, 7) #define MT_WTBL2_W14_CC_NOISE_3S GENMASK(20, 14) #define MT_WTBL2_W14_CHAN_EST_RMS GENMASK(24, 21) #define MT_WTBL2_W14_CC_NOISE_SEL BIT(15) #define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26) #define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(23, 0) #define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24) #define MT_WTBL1_OR (MT_WTBL1_BASE + 0x2300) #define MT_WTBL1_OR_PSM_WRITE BIT(31) #endif