diff --git a/mt7603.h b/mt7603.h
index 399fcc5f..1e69612c 100644
--- a/mt7603.h
+++ b/mt7603.h
@@ -18,6 +18,7 @@
 #include "mt7603_regs.h"
 
 #define MT7603_WTBL_SIZE	128
+#define MT7603_WTBL_RESERVED	(MT7603_WTBL_SIZE - 1)
 
 #define MT7603_FIRMWARE_E1	"mt7603_e1.bin"
 #define MT7603_FIRMWARE_E2	"mt7603_e2.bin"
@@ -111,6 +112,7 @@ int mt7603_set_channel(struct mt7603_dev *dev, struct cfg80211_chan_def *def);
 int mt7603_mcu_set_channel(struct mt7603_dev *dev);
 int mt7603_mcu_reg_read(struct mt7603_dev *dev, u32 reg, u32 *val, bool rf);
 
+void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, const u8 *addr);
 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
 
 #endif
diff --git a/mt7603_init.c b/mt7603_init.c
index aaad1350..a98206b4 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/etherdevice.h>
 #include "mt7603.h"
 #include "mt7603_dma.h"
 
@@ -64,7 +65,7 @@ mt7603_mac_reset(struct mt7603_dev *dev)
 
 	/* Disable MAC */
 	mt76_set(dev, MT_WF_ARB_SCR, MT_WF_ARB_TX_DISABLE | MT_WF_ARB_RX_DISABLE);
-	mt76_wr(dev, MT_WF_ARB_TQCR0, 0);
+	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
 
 	mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, 0x400);
@@ -100,7 +101,7 @@ int mt7603_mac_start(struct mt7603_dev *dev)
 	udelay(50);
 
 	mt76_clear(dev, MT_WF_ARB_SCR, MT_WF_ARB_TX_DISABLE | MT_WF_ARB_RX_DISABLE);
-	mt76_wr(dev, MT_WF_ARB_TQCR0, ~0);
+	mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
 	mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
 
 	mt76_set(dev, MT_WPDMA_GLO_CFG,
@@ -198,10 +199,16 @@ mt7603_phy_init(struct mt7603_dev *dev)
 static void
 mt7603_mac_init(struct mt7603_dev *dev)
 {
+	u8 addr[ETH_ALEN];
 	int i;
 
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);
+
 	for (i = 0; i < MT7603_WTBL_SIZE; i++)
 		mt7603_wtbl_clear(dev, i);
+
+	eth_broadcast_addr(addr);
+	mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, addr);
 }
 
 static int
diff --git a/mt7603_mac.c b/mt7603_mac.c
index 446cc1c1..35d45644 100644
--- a/mt7603_mac.c
+++ b/mt7603_mac.c
@@ -15,6 +15,51 @@
 
 #define MT_PSE_PAGE_SIZE	128
 
+static u32
+mt7603_ac_queue_mask0(u32 mask)
+{
+	u32 ret = 0;
+
+	ret |= GENMASK(3, 0) * !!(mask & BIT(0));
+	ret |= GENMASK(8, 5) * !!(mask & BIT(1));
+	ret |= GENMASK(13, 10) * !!(mask & BIT(2));
+	ret |= GENMASK(19, 16) * !!(mask & BIT(3));
+	return ret;
+}
+
+static void
+mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
+{
+	mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
+}
+
+static void
+mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
+{
+	mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
+}
+
+static void
+mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
+{
+	mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
+		 MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
+
+	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
+}
+
+void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, const u8 *mac_addr)
+{
+	const void *_mac = mac_addr;
+	u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
+
+	mt76_set(dev, addr + 0 * 4,
+		 MT76_SET(MT_WTBL1_W0_ADDR_HI, get_unaligned_le16(_mac + 4)));
+	mt76_set(dev, addr + 1 * 4,
+		 MT76_SET(MT_WTBL1_W1_ADDR_LO, get_unaligned_le32(_mac)));
+	mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
+}
+
 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
 {
 	int wtbl2_frame = (idx * MT_WTBL2_SIZE) / MT_PSE_PAGE_SIZE;
@@ -23,15 +68,17 @@ void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
 	int wtbl3_entry = ((idx * MT_WTBL3_SIZE) % MT_PSE_PAGE_SIZE) * 2;
 	int wtbl4_frame = (idx * MT_WTBL4_SIZE) / MT_PSE_PAGE_SIZE;
 	int wtbl4_entry = (idx * MT_WTBL4_SIZE) % MT_PSE_PAGE_SIZE;
-	u32 addr;
-
-	addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
+	u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
+	int i;
 
 	mt76_wr(dev, addr + 0 * 4,
 		MT_WTBL1_W0_RX_CHECK_A2 |
 		MT_WTBL1_W0_RX_VALID);
 	mt76_wr(dev, addr + 1 * 4, 0);
 	mt76_wr(dev, addr + 2 * 4, 0);
+
+	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
+
 	mt76_wr(dev, addr + 3 * 4,
 		MT76_SET(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
 		MT76_SET(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
@@ -40,4 +87,22 @@ void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
 		MT76_SET(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
 		MT76_SET(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
 		MT76_SET(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
+
+	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
+
+	/* Mapped to WTBL2 */
+	addr = MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
+
+	/* Clear BA information */
+	mt76_wr(dev, addr + (15 * 4), 0);
+
+	mt76_stop_tx_ac(dev, GENMASK(3, 0));
+	for (i = 2; i <= 4; i++)
+		mt76_wr(dev, addr + (i * 4), 0);
+	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
+	mt76_start_tx_ac(dev, GENMASK(3, 0));
+
+	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
+	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
+	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
 }
diff --git a/mt7603_regs.h b/mt7603_regs.h
index 23c0b0af..a766dd42 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -152,7 +152,12 @@
 #define MT_WF_ARB_TX_DISABLE		BIT(8)
 #define MT_WF_ARB_RX_DISABLE		BIT(9)
 
-#define MT_WF_ARB_TQCR0			MT_WF_ARB(0x100)
+#define MT_WF_ARB_TX_START_0		MT_WF_ARB(0x100)
+#define MT_WF_ARB_TX_START_1		MT_WF_ARB(0x104)
+#define MT_WF_ARB_TX_FLUSH_0		MT_WF_ARB(0x108)
+#define MT_WF_ARB_TX_FLUSH_1		MT_WF_ARB(0x10c)
+#define MT_WF_ARB_TX_STOP_0		MT_WF_ARB(0x110)
+#define MT_WF_ARB_TX_STOP_1		MT_WF_ARB(0x114)
 
 #define MT_WF_TMAC_BASE			0x21600
 #define MT_WF_TMAC(ofs)			(MT_WF_TMAC_BASE + (ofs))
@@ -215,6 +220,20 @@
 #define MT_WF_RFCR1			MT_WF_RMAC(0x0a4)
 #define MT_WF_RMAC_TMR_PA		MT_WF_RMAC(0x0e0)
 
+#define MT_WTBL_OFF_BASE		0x23000
+#define MT_WTBL_OFF(n)			(MT_WTBL_OFF_BASE + (n))
+
+#define MT_WTBL_UPDATE			MT_WTBL_OFF(0x000)
+#define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(7, 0)
+#define MT_WTBL_UPDATE_WTBL2		BIT(11)
+#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR	BIT(12)
+#define MT_WTBL_UPDATE_RATE_UPDATE	BIT(13)
+#define MT_WTBL_UPDATE_TX_COUNT_CLEAR	BIT(14)
+#define MT_WTBL_UPDATE_RX_COUNT_CLEAR	BIT(15)
+#define MT_WTBL_UPDATE_BUSY		BIT(16)
+
+#define MT_WTBL_RMVTCR			MT_WTBL_OFF(0x008)
+
 #define MT_WTBL1_BASE			0x28000
 
 #define MT_PCIE_REMAP_BASE_1		0x40000
@@ -369,4 +388,7 @@
 #define MT_WTBL2_W15_BA_WIN_SIZE	GENMASK(23, 0)
 #define MT_WTBL2_W15_BA_EN_TIDS		GENMASK(31, 24)
 
+#define MT_WTBL1_OR			(MT_WTBL1_BASE + 0x2300)
+#define MT_WTBL1_OR_PSM_WRITE		BIT(31)
+
 #endif