diff --git a/Makefile b/Makefile
index f7bfc39e..6477af8c 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@ EXTRA_CFLAGS += -Werror
 obj-m := mt76.o mt76x2e.o
 
 mt76-y := \
-	util.o
+	mmio.o util.o trace.o
 
 mt76x2e-y := \
 	mt76x2_pci.o mt76x2_dma.o \
diff --git a/mmio.c b/mmio.c
new file mode 100644
index 00000000..dd7c1f3d
--- /dev/null
+++ b/mmio.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "mt76.h"
+#include "trace.h"
+
+static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset)
+{
+	u32 val;
+
+	val = ioread32(dev->regs + offset);
+	trace_reg_read(dev, offset, val);
+
+	return val;
+}
+
+static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
+{
+	trace_reg_write(dev, offset, val);
+	iowrite32(val, dev->regs + offset);
+}
+
+static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
+{
+	val |= mt76_mmio_rr(dev, offset) & ~mask;
+	mt76_mmio_wr(dev, offset, val);
+	return val;
+}
+
+static void mt76_mmio_copy(struct mt76_dev *dev, u32 offset, const void *data, int len)
+{
+	__iowrite32_copy(dev->regs + offset, data, len >> 2);
+}
+
+void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
+{
+	static const struct mt76_bus_ops mt76_mmio_ops = {
+		.rr = mt76_mmio_rr,
+		.rmw = mt76_mmio_rmw,
+		.wr = mt76_mmio_wr,
+		.copy = mt76_mmio_copy,
+	};
+
+	dev->bus = &mt76_mmio_ops;
+	dev->regs = regs;
+}
+EXPORT_SYMBOL_GPL(mt76_mmio_init);
diff --git a/mt76.h b/mt76.h
new file mode 100644
index 00000000..aa5d7f9b
--- /dev/null
+++ b/mt76.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MT76_H
+#define __MT76_H
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <net/mac80211.h>
+#include "util.h"
+
+struct mt76_dev;
+
+struct mt76_bus_ops {
+	u32 (*rr)(struct mt76_dev *dev, u32 offset);
+	void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
+	u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
+	void (*copy)(struct mt76_dev *dev, u32 offset, const void *data, int len);
+};
+
+struct mt76_dev {
+	const struct mt76_bus_ops *bus;
+	void __iomem *regs;
+
+	struct ieee80211_hw *hw;
+};
+
+#define mt76_rr(dev, ...)	(dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
+#define mt76_wr(dev, ...)	(dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
+#define mt76_rmw(dev, ...)	(dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
+#define mt76_wr_copy(dev, ...)	(dev)->mt76.bus->copy(&((dev)->mt76), __VA_ARGS__)
+
+#define mt76_hw(dev) (dev)->mt76.hw
+
+void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
+
+#endif
diff --git a/mt76x2.h b/mt76x2.h
index 689b939b..d450e803 100644
--- a/mt76x2.h
+++ b/mt76x2.h
@@ -14,9 +14,7 @@
 #ifndef __MT76x2_H
 #define __MT76x2_H
 
-#include <linux/kernel.h>
 #include <linux/device.h>
-#include <linux/io.h>
 #include <linux/dma-mapping.h>
 #include <linux/spinlock.h>
 #include <linux/skbuff.h>
@@ -26,7 +24,6 @@
 #include <linux/mutex.h>
 #include <linux/bitops.h>
 #include <linux/kfifo.h>
-#include <net/mac80211.h>
 
 #define MT7662_FIRMWARE		"mt7662.bin"
 #define MT7662_ROM_PATCH	"mt7662_rom_patch.bin"
@@ -44,8 +41,8 @@
 
 #define MT_CALIBRATE_INTERVAL	HZ
 
+#include "mt76.h"
 #include "mt76x2_regs.h"
-#include "util.h"
 #include "mt76x2_mac.h"
 
 struct mt76x2_queue_entry {
@@ -168,13 +165,12 @@ struct mt76x2_dma_ops {
 };
 
 struct mt76x2_dev {
-	struct ieee80211_hw *hw;
+	struct mt76_dev mt76;
+
 	struct device *dev;
 	u8 macaddr[ETH_ALEN];
 	struct mac_address macaddr_list[8];
 
-	void __iomem *regs;
-
 	struct mutex mutex;
 
 	const struct mt76x2_dma_ops *dma_ops;
@@ -268,34 +264,27 @@ struct mt76x2_reg_pair {
 	u32 value;
 };
 
-#define mt76_hw(dev) (dev)->hw
-
-u32 mt76x2_rr(struct mt76x2_dev *dev, u32 offset);
-void mt76x2_wr(struct mt76x2_dev *dev, u32 offset, u32 val);
-u32 mt76x2_rmw(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val);
-void mt76x2_wr_copy(struct mt76x2_dev *dev, u32 offset, const void *data, int len);
-
 bool mt76x2_poll(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
 	       int timeout);
 bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
 		    int timeout);
-void mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
+void mt76_write_reg_pairs(struct mt76x2_dev *dev,
 			  const struct mt76x2_reg_pair *data, int len);
 
 #define mt76x2_get_field(_dev, _reg, _field)		\
-	MT76_GET(_field, mt76x2_rr(dev, _reg))
+	MT76_GET(_field, mt76_rr(dev, _reg))
 
-#define mt76x2_rmw_field(_dev, _reg, _field, _val)	\
-	mt76x2_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
+#define mt76_rmw_field(_dev, _reg, _field, _val)	\
+	mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
 
 static inline u32 mt76x2_set(struct mt76x2_dev *dev, u32 offset, u32 val)
 {
-	return mt76x2_rmw(dev, offset, 0, val);
+	return mt76_rmw(dev, offset, 0, val);
 }
 
 static inline u32 mt76x2_clear(struct mt76x2_dev *dev, u32 offset, u32 val)
 {
-	return mt76x2_rmw(dev, offset, val, 0);
+	return mt76_rmw(dev, offset, val, 0);
 }
 
 static inline bool is_mt7612(struct mt76x2_dev *dev)
diff --git a/mt76x2_core.c b/mt76x2_core.c
index 34ea9183..507e63ff 100644
--- a/mt76x2_core.c
+++ b/mt76x2_core.c
@@ -22,7 +22,7 @@ bool mt76x2_poll(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
 
 	timeout /= 10;
 	do {
-		cur = mt76x2_rr(dev, offset) & mask;
+		cur = mt76_rr(dev, offset) & mask;
 		if (cur == val)
 			return true;
 
@@ -39,7 +39,7 @@ bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
 
 	timeout /= 10;
 	do {
-		cur = mt76x2_rr(dev, offset) & mask;
+		cur = mt76_rr(dev, offset) & mask;
 		if (cur == val)
 			return true;
 
@@ -49,11 +49,11 @@ bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
 	return false;
 }
 
-void mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
+void mt76_write_reg_pairs(struct mt76x2_dev *dev,
 			  const struct mt76x2_reg_pair *data, int len)
 {
 	while (len > 0) {
-		mt76x2_wr(dev, data->reg, data->value);
+		mt76_wr(dev, data->reg, data->value);
 		len--;
 		data++;
 	}
@@ -66,7 +66,7 @@ void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set)
 	spin_lock_irqsave(&dev->irq_lock, flags);
 	dev->irqmask &= ~clear;
 	dev->irqmask |= set;
-	mt76x2_wr(dev, MT_INT_MASK_CSR, dev->irqmask);
+	mt76_wr(dev, MT_INT_MASK_CSR, dev->irqmask);
 	spin_unlock_irqrestore(&dev->irq_lock, flags);
 }
 
@@ -75,8 +75,8 @@ irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance)
 	struct mt76x2_dev *dev = dev_instance;
 	u32 intr;
 
-	intr = mt76x2_rr(dev, MT_INT_SOURCE_CSR);
-	mt76x2_wr(dev, MT_INT_SOURCE_CSR, intr);
+	intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
+	mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
 
 	if (!test_bit(MT76_STATE_INITIALIZED, &dev->state))
 		return IRQ_NONE;
diff --git a/mt76x2_debugfs.c b/mt76x2_debugfs.c
index cc2ca9a0..64d8aaed 100644
--- a/mt76x2_debugfs.c
+++ b/mt76x2_debugfs.c
@@ -19,7 +19,7 @@ mt76x2_reg_set(void *data, u64 val)
 {
 	struct mt76x2_dev *dev = data;
 
-	mt76x2_wr(dev, dev->debugfs_reg, val);
+	mt76_wr(dev, dev->debugfs_reg, val);
 	return 0;
 }
 
@@ -28,7 +28,7 @@ mt76x2_reg_get(void *data, u64 *val)
 {
 	struct mt76x2_dev *dev = data;
 
-	*val = mt76x2_rr(dev, dev->debugfs_reg);
+	*val = mt76_rr(dev, dev->debugfs_reg);
 	return 0;
 }
 
diff --git a/mt76x2_dma.c b/mt76x2_dma.c
index c466ba70..d2d05621 100644
--- a/mt76x2_dma.c
+++ b/mt76x2_dma.c
@@ -406,7 +406,7 @@ mt76x2_init_tx_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q,
 {
 	int ret;
 
-	q->regs = dev->regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
+	q->regs = dev->mt76.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
 	q->ndesc = n_desc;
 
 	ret = mt76x2_alloc_queue(dev, q);
@@ -490,7 +490,7 @@ mt76x2_init_rx_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q,
 {
 	int ret;
 
-	q->regs = dev->regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
+	q->regs = dev->mt76.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
 	q->ndesc = n_desc;
 	q->buf_size = bufsize;
 
@@ -580,7 +580,7 @@ int mt76x2_dma_init(struct mt76x2_dev *dev)
 	tasklet_init(&dev->tx_tasklet, mt76x2_tx_tasklet, (unsigned long) dev);
 	tasklet_init(&dev->rx_tasklet, mt76x2_rx_tasklet, (unsigned long) dev);
 
-	mt76x2_wr(dev, MT_WPDMA_RST_IDX, ~0);
+	mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
 
 	for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
 		ret = mt76x2_init_tx_queue(dev, &dev->q_tx[i], wmm_queue_map[i],
diff --git a/mt76x2_eeprom.c b/mt76x2_eeprom.c
index ae186b53..4bbb0c48 100644
--- a/mt76x2_eeprom.c
+++ b/mt76x2_eeprom.c
@@ -64,26 +64,26 @@ mt76x2_efuse_read(struct mt76x2_dev *dev, u16 addr, u8 *data)
 	u32 val;
 	int i;
 
-	val = mt76x2_rr(dev, MT_EFUSE_CTRL);
+	val = mt76_rr(dev, MT_EFUSE_CTRL);
 	val &= ~(MT_EFUSE_CTRL_AIN |
 		 MT_EFUSE_CTRL_MODE);
 	val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf);
 	val |= MT_EFUSE_CTRL_KICK;
-	mt76x2_wr(dev, MT_EFUSE_CTRL, val);
+	mt76_wr(dev, MT_EFUSE_CTRL, val);
 
 	if (!mt76x2_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
 		return -ETIMEDOUT;
 
 	udelay(2);
 
-	val = mt76x2_rr(dev, MT_EFUSE_CTRL);
+	val = mt76_rr(dev, MT_EFUSE_CTRL);
 	if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
 		memset(data, 0xff, 16);
 		return 0;
 	}
 
 	for (i = 0; i < 4; i++) {
-	    val = mt76x2_rr(dev, MT_EFUSE_DATA(i));
+	    val = mt76_rr(dev, MT_EFUSE_DATA(i));
 	    put_unaligned_le32(val, data + 4 * i);
 	}
 
diff --git a/mt76x2_init.c b/mt76x2_init.c
index 2cc8300b..68dddc6d 100644
--- a/mt76x2_init.c
+++ b/mt76x2_init.c
@@ -22,7 +22,7 @@ mt76x2_wait_for_mac(struct mt76x2_dev *dev)
 	int i;
 
 	for (i = 0; i < 500; i++) {
-		switch (mt76x2_rr(dev, MT_MAC_CSR0)) {
+		switch (mt76_rr(dev, MT_MAC_CSR0)) {
 		case 0:
 		case ~0:
 			break;
@@ -58,12 +58,12 @@ mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
 	mt76x2_set(dev, MT_PBF_SYS_CTRL, val);
 	mt76x2_clear(dev, MT_PBF_SYS_CTRL, val);
 
-	mt76x2_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
-	mt76x2_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
+	mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
+	mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
 }
 
 static void
-mt76x2_write_mac_initvals(struct mt76x2_dev *dev)
+mt76_write_mac_initvals(struct mt76x2_dev *dev)
 {
 	static const struct mt76x2_reg_pair vals[] = {
 		/* Copied from MediaTek reference source */
@@ -122,7 +122,7 @@ mt76x2_write_mac_initvals(struct mt76x2_dev *dev)
 		{ MT_HT_CTRL_CFG,		0x000001ff },
 	};
 
-	mt76x2_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
+	mt76_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
 }
 
 static void
@@ -149,16 +149,16 @@ mt76x2_fixup_xtal(struct mt76x2_dev *dev)
 	}
 
 	eep_val &= 0x7f;
-	mt76x2_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
+	mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
 	mt76x2_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
 
 	eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
 	switch (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
 	case 0:
-		mt76x2_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
+		mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
 		break;
 	case 1:
-		mt76x2_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
+		mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
 		break;
 	default:
 		break;
@@ -179,7 +179,7 @@ mt76x2_init_beacon_offsets(struct mt76x2_dev *dev)
 	}
 
 	for (i = 0; i < 4; i++)
-		mt76x2_wr(dev, MT_BCN_OFFSET(i), regs[i]);
+		mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
 }
 
 int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
@@ -191,7 +191,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
 	if (!mt76x2_wait_for_mac(dev))
 		return -ETIMEDOUT;
 
-	val = mt76x2_rr(dev, MT_WPDMA_GLO_CFG);
+	val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
 
 	val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
 		 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
@@ -200,10 +200,10 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
 		 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
 	val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
 
-	mt76x2_wr(dev, MT_WPDMA_GLO_CFG, val);
+	mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
 
 	mt76x2_mac_pbf_init(dev);
-	mt76x2_write_mac_initvals(dev);
+	mt76_write_mac_initvals(dev);
 	mt76x2_fixup_xtal(dev);
 
 	mt76x2_clear(dev, MT_MAC_SYS_CTRL,
@@ -216,28 +216,28 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
 	mt76x2_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
 	mt76x2_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
 
-	mt76x2_wr(dev, MT_RF_BYPASS_0, 0x06000000);
-	mt76x2_wr(dev, MT_RF_SETTING_0, 0x08800000);
+	mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
+	mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
 	msleep(5);
-	mt76x2_wr(dev, MT_RF_BYPASS_0, 0x00000000);
+	mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
 
-	mt76x2_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
+	mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
 	mt76x2_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
 
-	mt76x2_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
-	mt76x2_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
+	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
+	mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
 
-	mt76x2_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr));
-	mt76x2_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) |
+	mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr));
+	mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) |
 		MT76_SET(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
 		MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
 
 	/* Fire a pre-TBTT interrupt 8 ms before TBTT */
-	mt76x2_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
+	mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
 		       8 << 4);
-	mt76x2_wr(dev, MT_INT_TIMER_EN, 0);
+	mt76_wr(dev, MT_INT_TIMER_EN, 0);
 
-	mt76x2_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
+	mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
 	if (!hard)
 		return 0;
 
@@ -254,7 +254,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
 	}
 
 	for (i = 0; i < 16; i++)
-		mt76x2_rr(dev, MT_TX_STAT_FIFO);
+		mt76_rr(dev, MT_TX_STAT_FIFO);
 
 	mt76x2_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
 	mt76x2_init_beacon_offsets(dev);
@@ -269,14 +269,14 @@ int mt76x2_mac_start(struct mt76x2_dev *dev)
 	int i;
 
 	for (i = 0; i < 16; i++)
-		mt76x2_rr(dev, MT_TX_AGG_CNT(i));
+		mt76_rr(dev, MT_TX_AGG_CNT(i));
 
 	for (i = 0; i < 16; i++)
-		mt76x2_rr(dev, MT_TX_STAT_FIFO);
+		mt76_rr(dev, MT_TX_STAT_FIFO);
 
 	memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
 
-	mt76x2_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
+	mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
 	wait_for_wpdma(dev);
 	udelay(50);
 
@@ -286,9 +286,9 @@ int mt76x2_mac_start(struct mt76x2_dev *dev)
 
 	mt76x2_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
 
-	mt76x2_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
+	mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
 
-	mt76x2_wr(dev, MT_MAC_SYS_CTRL,
+	mt76_wr(dev, MT_MAC_SYS_CTRL,
 		MT_MAC_SYS_CTRL_ENABLE_TX |
 		MT_MAC_SYS_CTRL_ENABLE_RX);
 
@@ -303,18 +303,18 @@ void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
 	u32 rts_cfg;
 	int i;
 
-	mt76x2_wr(dev, MT_MAC_SYS_CTRL, 0);
+	mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
 
-	rts_cfg = mt76x2_rr(dev, MT_TX_RTS_CFG);
-	mt76x2_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
+	rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
+	mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
 
 	/* Wait for MAC to become idle */
 	for (i = 0; i < 300; i++) {
-		if (mt76x2_rr(dev, MT_MAC_STATUS) &
+		if (mt76_rr(dev, MT_MAC_STATUS) &
 		    (MT_MAC_STATUS_RX | MT_MAC_STATUS_TX))
 			continue;
 
-		if (mt76x2_rr(dev, MT_BBP(IBI, 12)))
+		if (mt76_rr(dev, MT_BBP(IBI, 12)))
 			continue;
 
 		stopped = true;
@@ -329,12 +329,12 @@ void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
 		mt76x2_clear(dev, MT_BBP(CORE, 4), BIT(0));
 	}
 
-	mt76x2_wr(dev, MT_TX_RTS_CFG, rts_cfg);
+	mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
 }
 
 void mt76x2_mac_resume(struct mt76x2_dev *dev)
 {
-	mt76x2_wr(dev, MT_MAC_SYS_CTRL,
+	mt76_wr(dev, MT_MAC_SYS_CTRL,
 		MT_MAC_SYS_CTRL_ENABLE_TX |
 		MT_MAC_SYS_CTRL_ENABLE_RX);
 }
@@ -349,7 +349,7 @@ mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
 	mt76x2_clear(dev, 0x1001c, 0xff);
 	mt76x2_set(dev, 0x1001c, 0x30);
 
-	mt76x2_wr(dev, 0x10014, 0x484f);
+	mt76_wr(dev, 0x10014, 0x484f);
 	udelay(1);
 
 	mt76x2_set(dev, 0x10130, BIT(17));
@@ -429,14 +429,14 @@ void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
 			      MT_XIFS_TIME_CFG_OFDM_SIFS);
 
 	ackto = slottime + sifs;
-	mt76x2_rmw_field(dev, MT_TX_TIMEOUT_CFG,
+	mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
 		       MT_TX_TIMEOUT_CFG_ACKTO, ackto);
 }
 
 static void
 mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
 {
-	u32 val = mt76x2_rr(dev, MT_WLAN_FUN_CTRL);
+	u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
 
 	if (enable)
 		val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
@@ -445,7 +445,7 @@ mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
 		val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
 			 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
 
-	mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
+	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
 	udelay(20);
 }
 
@@ -454,19 +454,19 @@ mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable)
 {
 	u32 val;
 
-	val = mt76x2_rr(dev, MT_WLAN_FUN_CTRL);
+	val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
 
 	val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
 
 	if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
 		val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
-		mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
+		mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
 		udelay(20);
 
 		val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
 	}
 
-	mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
+	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
 	udelay(20);
 
 	mt76x2_set_wlan_state(dev, enable);
@@ -506,12 +506,12 @@ int mt76x2_init_hardware(struct mt76x2_dev *dev)
 
 	dev->slottime = 9;
 
-	val = mt76x2_rr(dev, MT_WPDMA_GLO_CFG);
+	val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
 	val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
 	       MT_WPDMA_GLO_CFG_BIG_ENDIAN |
 	       MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
 	val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
-	mt76x2_wr(dev, MT_WPDMA_GLO_CFG, val);
+	mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
 
 	mt76x2_reset_wlan(dev, true);
 	mt76x2_power_on(dev);
@@ -538,7 +538,7 @@ int mt76x2_init_hardware(struct mt76x2_dev *dev)
 		return ret;
 
 	mt76x2_mac_stop(dev, false);
-	dev->rxfilter = mt76x2_rr(dev, MT_RX_FILTR_CFG);
+	dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
 
 	return 0;
 }
@@ -569,7 +569,7 @@ struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
 
 	dev = hw->priv;
 	dev->dev = pdev;
-	dev->hw = hw;
+	dev->mt76.hw = hw;
 	mutex_init(&dev->mutex);
 	spin_lock_init(&dev->lock);
 	spin_lock_init(&dev->irq_lock);
diff --git a/mt76x2_mac.c b/mt76x2_mac.c
index 74997a5a..6d0b5d4e 100644
--- a/mt76x2_mac.c
+++ b/mt76x2_mac.c
@@ -20,8 +20,8 @@
 void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr)
 {
 	idx &= 7;
-	mt76x2_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
-	mt76x2_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
+	mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
+	mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
 		       get_unaligned_le16(addr + 4));
 }
 
@@ -412,13 +412,13 @@ void mt76x2_mac_poll_tx_status(struct mt76x2_dev *dev, bool irq)
 		u32 stat1, stat2;
 
 		spin_lock_irqsave(&dev->irq_lock, flags);
-		stat1 = mt76x2_rr(dev, MT_TX_STAT_FIFO);
+		stat1 = mt76_rr(dev, MT_TX_STAT_FIFO);
 		if (!(stat1 & MT_TX_STAT_FIFO_VALID)) {
 			spin_unlock_irqrestore(&dev->irq_lock, flags);
 			break;
 		}
 
-		stat2 = mt76x2_rr(dev, MT_TX_STAT_FIFO_EXT);
+		stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT);
 		spin_unlock_irqrestore(&dev->irq_lock, flags);
 
 		stat.valid = 1;
@@ -498,12 +498,12 @@ void mt76x2_mac_wcid_setup(struct mt76x2_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
 	attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
 	       MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
 
-	mt76x2_wr(dev, MT_WCID_ATTR(idx), attr);
+	mt76_wr(dev, MT_WCID_ATTR(idx), attr);
 
 	if (mac)
 		memcpy(addr.macaddr, mac, ETH_ALEN);
 
-	mt76x2_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
+	mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
 }
 
 int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx,
@@ -517,19 +517,19 @@ int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx,
 	if (cipher == MT_CIPHER_NONE && key)
 		return -EINVAL;
 
-	mt76x2_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
-	mt76x2_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
+	mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
+	mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
 
 	memset(iv_data, 0, sizeof(iv_data));
 	if (key) {
-		mt76x2_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
+		mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
 			       !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 		iv_data[3] = key->keyidx << 6;
 		if (cipher >= MT_CIPHER_TKIP)
 			iv_data[3] |= 0x20;
 	}
 
-	mt76x2_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
+	mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
 
 	return 0;
 }
@@ -545,12 +545,12 @@ int mt76x2_mac_shared_key_setup(struct mt76x2_dev *dev, u8 vif_idx, u8 key_idx,
 	if (cipher == MT_CIPHER_NONE && key)
 		return -EINVAL;
 
-	val = mt76x2_rr(dev, MT_SKEY_MODE(vif_idx));
+	val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
 	val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
 	val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
-	mt76x2_wr(dev, MT_SKEY_MODE(vif_idx), val);
+	mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
 
-	mt76x2_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, sizeof(key_data));
+	mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, sizeof(key_data));
 
 	return 0;
 }
@@ -576,7 +576,7 @@ int mt76x2_mac_skb_tx_overhead(struct mt76x2_dev *dev, struct sk_buff *skb)
 }
 
 static int
-mt76x2_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
+mt76_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
 {
 	int beacon_len = dev->beacon_offsets[1] - dev->beacon_offsets[0];
 	struct mt76x2_txwi txwi;
@@ -587,10 +587,10 @@ mt76x2_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
 	mt76x2_mac_write_txwi(dev, &txwi, skb, NULL, NULL);
 	txwi.flags |= cpu_to_le16(MT_TXWI_FLAGS_TS);
 
-	mt76x2_wr_copy(dev, offset, &txwi, sizeof(txwi));
+	mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
 	offset += sizeof(txwi);
 
-	mt76x2_wr_copy(dev, offset, skb->data, skb->len);
+	mt76_wr_copy(dev, offset, skb->data, skb->len);
 	return 0;
 }
 
@@ -606,16 +606,16 @@ __mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 bcn_idx, struct sk_buff *skb)
 	mt76x2_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
 
 	if (skb) {
-		ret = mt76x2_write_beacon(dev, beacon_addr, skb);
+		ret = mt76_write_beacon(dev, beacon_addr, skb);
 		if (!ret)
 			dev->beacon_data_mask |= BIT(bcn_idx) & dev->beacon_mask;
 	} else {
 		dev->beacon_data_mask &= ~BIT(bcn_idx);
 		for (i = 0; i < beacon_len; i += 4)
-			mt76x2_wr(dev, beacon_addr + i, 0);
+			mt76_wr(dev, beacon_addr + i, 0);
 	}
 
-	mt76x2_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask);
+	mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask);
 
 	return ret;
 }
@@ -649,7 +649,7 @@ int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx, struct sk_buff *sk
 		__mt76x2_mac_set_beacon(dev, i, NULL);
 	}
 
-	mt76x2_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, bcn_idx - 1);
+	mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, bcn_idx - 1);
 	return 0;
 }
 
@@ -671,11 +671,11 @@ void mt76x2_mac_set_beacon_enable(struct mt76x2_dev *dev, u8 vif_idx, bool val)
 
 	en = dev->beacon_mask;
 
-	mt76x2_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
+	mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
 	reg = MT_BEACON_TIME_CFG_BEACON_TX |
 	      MT_BEACON_TIME_CFG_TBTT_EN |
 	      MT_BEACON_TIME_CFG_TIMER_EN;
-	mt76x2_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
+	mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
 
 	if (en)
 		mt76x2_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
@@ -690,7 +690,7 @@ void mt76x2_mac_work(struct work_struct *work)
 	int i, idx;
 
 	for (i = 0, idx = 0; i < 16; i++) {
-		u32 val = mt76x2_rr(dev, MT_TX_AGG_CNT(i));
+		u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
 		dev->aggr_stats[idx++] += val & 0xffff;
 		dev->aggr_stats[idx++] += val >> 16;
 	}
diff --git a/mt76x2_main.c b/mt76x2_main.c
index ee78eb7d..da958a26 100644
--- a/mt76x2_main.c
+++ b/mt76x2_main.c
@@ -149,7 +149,7 @@ mt76x2_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
 	MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL);
 
 	*total_flags = flags;
-	mt76x2_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
+	mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
 
 	mutex_unlock(&dev->mutex);
 }
@@ -167,7 +167,7 @@ mt76x2_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 		mt76x2_mac_set_bssid(dev, mvif->idx, info->bssid);
 
 	if (changed & BSS_CHANGED_BEACON_INT)
-		mt76x2_rmw_field(dev, MT_BEACON_TIME_CFG,
+		mt76_rmw_field(dev, MT_BEACON_TIME_CFG,
 			       MT_BEACON_TIME_CFG_INTVAL,
 			       info->beacon_int << 4);
 
@@ -181,7 +181,7 @@ mt76x2_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 		int slottime = info->use_short_slot ? 9 : 20;
 
 		dev->slottime = slottime;
-		mt76x2_rmw_field(dev, MT_BKOFF_SLOT_CFG,
+		mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
 			       MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
 	}
 
@@ -338,27 +338,27 @@ mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
 	      MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) |
 	      MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) |
 	      MT76_SET(MT_EDCA_CFG_CWMAX, cw_max);
-	mt76x2_wr(dev, MT_EDCA_CFG_AC(queue), val);
+	mt76_wr(dev, MT_EDCA_CFG_AC(queue), val);
 
-	val = mt76x2_rr(dev, MT_WMM_TXOP(queue));
+	val = mt76_rr(dev, MT_WMM_TXOP(queue));
 	val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue));
 	val |= params->txop << MT_WMM_TXOP_SHIFT(queue);
-	mt76x2_wr(dev, MT_WMM_TXOP(queue), val);
+	mt76_wr(dev, MT_WMM_TXOP(queue), val);
 
-	val = mt76x2_rr(dev, MT_WMM_AIFSN);
+	val = mt76_rr(dev, MT_WMM_AIFSN);
 	val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue));
 	val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue);
-	mt76x2_wr(dev, MT_WMM_AIFSN, val);
+	mt76_wr(dev, MT_WMM_AIFSN, val);
 
-	val = mt76x2_rr(dev, MT_WMM_CWMIN);
+	val = mt76_rr(dev, MT_WMM_CWMIN);
 	val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue));
 	val |= cw_min << MT_WMM_CWMIN_SHIFT(queue);
-	mt76x2_wr(dev, MT_WMM_CWMIN, val);
+	mt76_wr(dev, MT_WMM_CWMIN, val);
 
-	val = mt76x2_rr(dev, MT_WMM_CWMAX);
+	val = mt76_rr(dev, MT_WMM_CWMAX);
 	val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue));
 	val |= cw_max << MT_WMM_CWMAX_SHIFT(queue);
-	mt76x2_wr(dev, MT_WMM_CWMAX, val);
+	mt76_wr(dev, MT_WMM_CWMAX, val);
 
 	return 0;
 }
diff --git a/mt76x2_mcu.c b/mt76x2_mcu.c
index 168f06da..19e8f638 100644
--- a/mt76x2_mcu.c
+++ b/mt76x2_mcu.c
@@ -109,12 +109,6 @@ out:
 	return ret;
 }
 
-static void
-write_data(struct mt76x2_dev *dev, u32 offset, __le32 *data, int len)
-{
-	__iowrite32_copy(dev->regs + offset, data, len / 4);
-}
-
 static int
 mt76pci_load_rom_patch(struct mt76x2_dev *dev)
 {
@@ -138,7 +132,7 @@ mt76pci_load_rom_patch(struct mt76x2_dev *dev)
 		patch_reg = MT_MCU_COM_REG0;
 	}
 
-	if (rom_protect && (mt76x2_rr(dev, patch_reg) & patch_mask)) {
+	if (rom_protect && (mt76_rr(dev, patch_reg) & patch_mask)) {
 		printk("ROM patch already applied\n");
 		goto out;
 	}
@@ -156,16 +150,16 @@ mt76pci_load_rom_patch(struct mt76x2_dev *dev)
 	hdr = (struct mt76x2_patch_header *) fw->data;
 	printk("ROM patch build: %.15s\n", hdr->build_time);
 
-	mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ROM_PATCH_OFFSET);
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ROM_PATCH_OFFSET);
 
 	cur = (__le32 *) (fw->data + sizeof(*hdr));
 	len = fw->size - sizeof(*hdr);
-	write_data(dev, MT_MCU_ROM_PATCH_ADDR, cur, len);
+	mt76_wr_copy(dev, MT_MCU_ROM_PATCH_ADDR, cur, len);
 
-	mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
 
 	/* Trigger ROM */
-	mt76x2_wr(dev, MT_MCU_INT_LEVEL, 4);
+	mt76_wr(dev, MT_MCU_INT_LEVEL, 4);
 
 	if (!mt76x2_poll_msec(dev, patch_reg, patch_mask, patch_mask, 2000)) {
 		printk("Failed to load ROM patch\n");
@@ -175,7 +169,7 @@ mt76pci_load_rom_patch(struct mt76x2_dev *dev)
 out:
 	/* release semaphore */
 	if (rom_protect)
-		mt76x2_wr(dev, MT_MCU_SEMAPHORE_03, 1);
+		mt76_wr(dev, MT_MCU_SEMAPHORE_03, 1);
 	release_firmware(fw);
 	return ret;
 }
@@ -216,8 +210,8 @@ mt76pci_load_firmware(struct mt76x2_dev *dev)
 	cur = (__le32 *) (fw->data + sizeof(*hdr));
 	len = le32_to_cpu(hdr->ilm_len);
 
-	mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ILM_OFFSET);
-	write_data(dev, MT_MCU_ILM_ADDR, cur, len);
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ILM_OFFSET);
+	mt76_wr_copy(dev, MT_MCU_ILM_ADDR, cur, len);
 
 	cur += len / sizeof(*cur);
 	len = le32_to_cpu(hdr->dlm_len);
@@ -227,19 +221,19 @@ mt76pci_load_firmware(struct mt76x2_dev *dev)
 	else
 		offset = MT_MCU_DLM_ADDR;
 
-	mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_DLM_OFFSET);
-	write_data(dev, offset, cur, len);
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_DLM_OFFSET);
+	mt76_wr_copy(dev, offset, cur, len);
 
-	mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
+	mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
 
 	val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
 	if (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
 		mt76x2_set(dev, MT_MCU_COM_REG0, BIT(30));
 
 	/* trigger firmware */
-	mt76x2_wr(dev, MT_MCU_INT_LEVEL, 2);
+	mt76_wr(dev, MT_MCU_INT_LEVEL, 2);
 	for (i = 200; i > 0; i--) {
-		val = mt76x2_rr(dev, MT_MCU_COM_REG0);
+		val = mt76_rr(dev, MT_MCU_COM_REG0);
 
 		if (val & 1)
 			break;
@@ -435,7 +429,7 @@ int mt76x2_mcu_init(struct mt76x2_dev *dev)
 
 int mt76x2_mcu_cleanup(struct mt76x2_dev *dev)
 {
-	mt76x2_wr(dev, MT_MCU_INT_LEVEL, 1);
+	mt76_wr(dev, MT_MCU_INT_LEVEL, 1);
 	msleep(20);
 
 	return 0;
diff --git a/mt76x2_pci.c b/mt76x2_pci.c
index bde52005..1c485b68 100644
--- a/mt76x2_pci.c
+++ b/mt76x2_pci.c
@@ -23,34 +23,6 @@ static const struct pci_device_id mt76pci_device_table[] = {
 	{ },
 };
 
-u32 mt76x2_rr(struct mt76x2_dev *dev, u32 offset)
-{
-	u32 val;
-
-	val = ioread32(dev->regs + offset);
-	trace_reg_read(dev, offset, val);
-
-	return val;
-}
-
-void mt76x2_wr(struct mt76x2_dev *dev, u32 offset, u32 val)
-{
-	trace_reg_write(dev, offset, val);
-	iowrite32(val, dev->regs + offset);
-}
-
-u32 mt76x2_rmw(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val)
-{
-	val |= mt76x2_rr(dev, offset) & ~mask;
-	mt76x2_wr(dev, offset, val);
-	return val;
-}
-
-void mt76x2_wr_copy(struct mt76x2_dev *dev, u32 offset, const void *data, int len)
-{
-	__iowrite32_copy(dev->regs + offset, data, len >> 2);
-}
-
 static int
 mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
@@ -75,11 +47,11 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (!dev)
 		return -ENOMEM;
 
-	dev->regs = pcim_iomap_table(pdev)[0];
+	mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
 
 	pci_set_drvdata(pdev, dev);
 
-	dev->rev = mt76x2_rr(dev, MT_ASIC_VERSION);
+	dev->rev = mt76_rr(dev, MT_ASIC_VERSION);
 	dev_printk(KERN_INFO, dev->dev, "ASIC revision: %08x\n", dev->rev);
 
 	ret = devm_request_irq(dev->dev, pdev->irq, mt76x2_irq_handler,
@@ -94,13 +66,13 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	/* Fix up ASPM configuration */
 
 	/* RG_SSUSB_G1_CDR_BIR_LTR = 0x9 */
-	mt76x2_rmw_field(dev, 0x15a10, 0x1f << 16, 0x9);
+	mt76_rmw_field(dev, 0x15a10, 0x1f << 16, 0x9);
 
 	/* RG_SSUSB_G1_CDR_BIC_LTR = 0xf */
-	mt76x2_rmw_field(dev, 0x15a0c, 0xf << 28, 0xf);
+	mt76_rmw_field(dev, 0x15a0c, 0xf << 28, 0xf);
 
 	/* RG_SSUSB_CDR_BR_PE1D = 0x3 */
-	mt76x2_rmw_field(dev, 0x15c58, 0x3 << 6, 0x3);
+	mt76_rmw_field(dev, 0x15c58, 0x3 << 6, 0x3);
 
 	return 0;
 
diff --git a/mt76x2_phy.c b/mt76x2_phy.c
index c33e9ed5..ba0b6b2e 100644
--- a/mt76x2_phy.c
+++ b/mt76x2_phy.c
@@ -27,7 +27,7 @@ mt76x2_phy_rf_op(struct mt76x2_dev *dev, bool idx, u16 offset, bool write)
 	if (write)
 		val |= MT_RF_CTRL_WRITE;
 
-	mt76x2_wr(dev, MT_RF_CTRL, val);
+	mt76_wr(dev, MT_RF_CTRL, val);
 
 	return mt76x2_poll(dev, MT_RF_CTRL, MT_RF_CTRL_BUSY, 0, 2000);
 }
@@ -38,14 +38,14 @@ mt76x2_phy_rf_read(struct mt76x2_dev *dev, bool idx, u16 offset, u32 *val)
 	if (!mt76x2_phy_rf_op(dev, idx, offset, false))
 		return -ETIMEDOUT;
 
-	*val = mt76x2_rr(dev, MT_RF_DATA_READ);
+	*val = mt76_rr(dev, MT_RF_DATA_READ);
 	return 0;
 }
 
 static int __maybe_unused
 mt76x2_phy_rf_write(struct mt76x2_dev *dev, bool idx, u16 offset, u32 val)
 {
-	mt76x2_wr(dev, MT_RF_DATA_WRITE, val);
+	mt76_wr(dev, MT_RF_DATA_WRITE, val);
 
 	if (!mt76x2_phy_rf_op(dev, idx, offset, true))
 		return -ETIMEDOUT;
@@ -58,9 +58,9 @@ mt76x2_adjust_lna_gain(struct mt76x2_dev *dev, int reg, s8 offset)
 {
 	s8 gain;
 
-	gain = MT76_GET(MT_BBP_AGC_LNA_GAIN, mt76x2_rr(dev, MT_BBP(AGC, reg)));
+	gain = MT76_GET(MT_BBP_AGC_LNA_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
 	gain -= offset / 2;
-	mt76x2_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_GAIN, gain);
+	mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_GAIN, gain);
 }
 
 static void
@@ -68,9 +68,9 @@ mt76x2_adjust_agc_gain(struct mt76x2_dev *dev, int reg, s8 offset)
 {
 	s8 gain;
 
-	gain = MT76_GET(MT_BBP_AGC_GAIN, mt76x2_rr(dev, MT_BBP(AGC, reg)));
+	gain = MT76_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
 	gain += offset;
-	mt76x2_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
+	mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
 }
 
 static void
@@ -183,24 +183,24 @@ void mt76x2_phy_set_txpower(struct mt76x2_dev *dev)
 	txp_1 = mt76x2_txpower_check(txp.chain[1].target_power +
 				   txp.chain[1].delta + delta);
 
-	mt76x2_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
-	mt76x2_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
+	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
+	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
 
-	mt76x2_wr(dev, MT_TX_PWR_CFG_0,
+	mt76_wr(dev, MT_TX_PWR_CFG_0,
 	        mt76x2_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_1,
+	mt76_wr(dev, MT_TX_PWR_CFG_1,
 	        mt76x2_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[2]));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_2,
+	mt76_wr(dev, MT_TX_PWR_CFG_2,
 	        mt76x2_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_3,
+	mt76_wr(dev, MT_TX_PWR_CFG_3,
 	        mt76x2_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_4,
+	mt76_wr(dev, MT_TX_PWR_CFG_4,
 	        mt76x2_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_7,
+	mt76_wr(dev, MT_TX_PWR_CFG_7,
 	        mt76x2_tx_power_mask(t.ofdm[4], t.vht[8], t.ht[6], t.vht[8]));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_8,
+	mt76_wr(dev, MT_TX_PWR_CFG_8,
 	        mt76x2_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
-	mt76x2_wr(dev, MT_TX_PWR_CFG_9,
+	mt76_wr(dev, MT_TX_PWR_CFG_9,
 	        mt76x2_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
 }
 
@@ -281,53 +281,53 @@ mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev, enum ieee80211_band band)
 		pa_mode[0] = 0x010055ff;
 		pa_mode[1] = 0x00550055;
 
-		mt76x2_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
-		mt76x2_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
+		mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
+		mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
 
 		if (mt76x2_ext_pa_enabled(dev, band)) {
-			mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
-			mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
+			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
+			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
 		} else {
-			mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
-			mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
+			mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
+			mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
 		}
 	} else {
 		pa_mode[0] = 0x0000ffff;
 		pa_mode[1] = 0x00ff00ff;
 
-		mt76x2_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
-		mt76x2_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
-		mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0);
+		mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
+		mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
+		mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
 
 		if (mt76x2_ext_pa_enabled(dev, band))
 			pa_mode_adj = 0x04000000;
 		else
 			pa_mode_adj = 0;
 
-		mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
-		mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
+		mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
+		mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
 	}
 
-	mt76x2_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
-	mt76x2_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
-	mt76x2_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
-	mt76x2_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
+	mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
+	mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
+	mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
+	mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
 
 	if (mt76x2_ext_pa_enabled(dev, band)) {
 		u32 val = 0x3c3c023c;
-		mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, val);
-		mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, val);
-		mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
+		mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
+		mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
+		mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
 	} else {
 		if (band == IEEE80211_BAND_2GHZ) {
 			u32 val = 0x0f3c3c3c;
-			mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, val);
-			mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, val);
-			mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
+			mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
+			mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
+			mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
 		} else {
-			mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
-			mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
-			mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0);
+			mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
+			mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
+			mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
 		}
 	}
 }
@@ -344,10 +344,10 @@ mt76x2_configure_tx_delay(struct mt76x2_dev *dev, enum ieee80211_band band, u8 b
 		cfg0 = bw ? 0x000b0b01 : 0x00101001;
 		cfg1 = 0x00021414;
 	}
-	mt76x2_wr(dev, MT_TX_SW_CFG0, cfg0);
-	mt76x2_wr(dev, MT_TX_SW_CFG1, cfg1);
+	mt76_wr(dev, MT_TX_SW_CFG0, cfg0);
+	mt76_wr(dev, MT_TX_SW_CFG1, cfg1);
 
-	mt76x2_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_CCK_SIFS,
+	mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_CCK_SIFS,
 		       13 + (bw ? 1 : 0));
 }
 
@@ -371,10 +371,10 @@ mt76x2_phy_set_bw(struct mt76x2_dev *dev, int width, u8 ctrl)
 		break;
 	}
 
-	mt76x2_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
-	mt76x2_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
-	mt76x2_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
-	mt76x2_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
+	mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
+	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
+	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
+	mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
 }
 
 static void
@@ -391,7 +391,7 @@ mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper)
 		break;
 	}
 
-	mt76x2_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
+	mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
 		       primary_upper);
 }
 
@@ -400,13 +400,13 @@ mt76x2_set_rx_chains(struct mt76x2_dev *dev)
 {
 	u32 val;
 
-	val = mt76x2_rr(dev, MT_BBP(AGC, 0));
+	val = mt76_rr(dev, MT_BBP(AGC, 0));
 	val &= ~(BIT(3) | BIT(4));
 
 	if (dev->chainmask & BIT(1))
 		val |= BIT(3);
 
-	mt76x2_wr(dev, MT_BBP(AGC, 0), val);
+	mt76_wr(dev, MT_BBP(AGC, 0), val);
 }
 
 static void
@@ -441,7 +441,7 @@ mt76x2_get_rssi_gain_thresh(struct mt76x2_dev *dev)
 static void
 mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
 {
-	u32 val = mt76x2_rr(dev, MT_BBP(AGC, 20));
+	u32 val = mt76_rr(dev, MT_BBP(AGC, 20));
 	int rssi0 = (s8) MT76_GET(MT_BBP_AGC20_RSSI0, val);
 	int rssi1 = (s8) MT76_GET(MT_BBP_AGC20_RSSI1, val);
 	bool low_gain;
@@ -465,26 +465,26 @@ mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
 	val |= 0xf8;
 
 	if (dev->chandef.width == NL80211_CHAN_WIDTH_80)
-		mt76x2_wr(dev, MT_BBP(RXO, 14), 0x00560411);
+		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560411);
 	else
-		mt76x2_wr(dev, MT_BBP(RXO, 14), 0x00560423);
+		mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
 
 	if (low_gain) {
-		mt76x2_wr(dev, MT_BBP(AGC, 35), 0x08080808);
-		mt76x2_wr(dev, MT_BBP(AGC, 37), 0x08080808);
+		mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
+		mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
 		if (mt76x2_has_ext_lna(dev))
 			gain_delta = 10;
 		else
 			gain_delta = 14;
 	} else {
-		mt76x2_wr(dev, MT_BBP(AGC, 35), 0x11111116);
-		mt76x2_wr(dev, MT_BBP(AGC, 37), 0x1010161C);
+		mt76_wr(dev, MT_BBP(AGC, 35), 0x11111116);
+		mt76_wr(dev, MT_BBP(AGC, 37), 0x1010161C);
 		gain_delta = 0;
 	}
 
-	mt76x2_wr(dev, MT_BBP(AGC, 8),
+	mt76_wr(dev, MT_BBP(AGC, 8),
 		val | MT76_SET(MT_BBP_AGC_GAIN, gain[0] - gain_delta));
-	mt76x2_wr(dev, MT_BBP(AGC, 9),
+	mt76_wr(dev, MT_BBP(AGC, 9),
 		val | MT76_SET(MT_BBP_AGC_GAIN, gain[1] - gain_delta));
 }
 
@@ -567,7 +567,7 @@ int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
 	mt76x2_phy_set_bw(dev, chandef->width, ch_group_index);
 	mt76x2_set_tx_dac(dev);
 
-	mt76x2_rmw(dev, MT_EXT_CCA_CFG,
+	mt76_rmw(dev, MT_EXT_CCA_CFG,
 		 (MT_EXT_CCA_CFG_CCA0 |
 		  MT_EXT_CCA_CFG_CCA1 |
 		  MT_EXT_CCA_CFG_CCA2 |
@@ -578,7 +578,7 @@ int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
 	if (chandef->width >= NL80211_CHAN_WIDTH_40)
 		sifs++;
 
-	mt76x2_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs);
+	mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs);
 
 	ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan);
 	if (ret)
@@ -605,11 +605,11 @@ int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
 
 	dev->cal.init_cal_done = true;
 
-	mt76x2_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
-	mt76x2_wr(dev, MT_BBP(AGC, 7), 0x08081010);
-	mt76x2_wr(dev, MT_BBP(AGC, 11), 0x00000404);
-	mt76x2_wr(dev, MT_BBP(AGC, 2), 0x00007070);
-	mt76x2_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
+	mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
+	mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
+	mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
+	mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
+	mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
 
 	if (scan)
 		return 0;
@@ -640,7 +640,7 @@ mt76x2_phy_tssi_compensate(struct mt76x2_dev *dev)
 		mt76x2_mcu_tssi_comp(dev, &t);
 		dev->cal.tssi_comp_pending = true;
 	} else {
-		if (mt76x2_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
+		if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
 			return;
 
 		dev->cal.tssi_comp_pending = false;
@@ -687,9 +687,9 @@ mt76x2_phy_temp_compensate(struct mt76x2_dev *dev)
 	db_diff = min(db_diff, t.upper_bound);
 	db_diff = max(db_diff, t.lower_bound);
 
-	mt76x2_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
+	mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
 		       db_diff * 2);
-	mt76x2_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
+	mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
 		       db_diff * 2);
 }
 
diff --git a/mt76x2_trace.h b/mt76x2_trace.h
index a5e6dfa5..506d85d1 100644
--- a/mt76x2_trace.h
+++ b/mt76x2_trace.h
@@ -31,11 +31,6 @@
 #define TXID_PR_FMT	" [%d:%d]"
 #define TXID_PR_ARG	__entry->wcid, __entry->pktid
 
-#define REG_ENTRY	__field(u32, reg) __field(u32, val)
-#define REG_ASSIGN	__entry->reg = reg; __entry->val = val
-#define REG_PR_FMT	" %04x=%08x"
-#define REG_PR_ARG	__entry->reg, __entry->val
-
 DECLARE_EVENT_CLASS(dev_evt,
 	TP_PROTO(struct mt76x2_dev *dev),
 	TP_ARGS(dev),
@@ -65,33 +60,6 @@ DECLARE_EVENT_CLASS(dev_txid_evt,
 	)
 );
 
-DECLARE_EVENT_CLASS(dev_reg_evt,
-	TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
-	TP_ARGS(dev, reg, val),
-	TP_STRUCT__entry(
-		DEV_ENTRY
-		REG_ENTRY
-	),
-	TP_fast_assign(
-		DEV_ASSIGN;
-		REG_ASSIGN;
-	),
-	TP_printk(
-		DEV_PR_FMT REG_PR_FMT,
-		DEV_PR_ARG, REG_PR_ARG
-	)
-);
-
-DEFINE_EVENT(dev_reg_evt, reg_read,
-	TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
-	TP_ARGS(dev, reg, val)
-);
-
-DEFINE_EVENT(dev_reg_evt, reg_write,
-	TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
-	TP_ARGS(dev, reg, val)
-);
-
 DEFINE_EVENT(dev_evt, mac_txstat_poll,
 	TP_PROTO(struct mt76x2_dev *dev),
 	TP_ARGS(dev)
diff --git a/trace.c b/trace.c
new file mode 100644
index 00000000..af424e46
--- /dev/null
+++ b/trace.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+
+#ifndef __CHECKER__
+#define CREATE_TRACE_POINTS
+#include "trace.h"
+
+#endif
diff --git a/trace.h b/trace.h
new file mode 100644
index 00000000..a25673a2
--- /dev/null
+++ b/trace.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#if !defined(__MT76_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define __MT76_TRACE_H
+
+#include <linux/tracepoint.h>
+#include "mt76.h"
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM mt76
+
+#define MAXNAME		32
+#define DEV_ENTRY   __array(char, wiphy_name, 32)
+#define DEV_ASSIGN  strlcpy(__entry->wiphy_name, wiphy_name(dev->hw->wiphy), MAXNAME)
+#define DEV_PR_FMT  "%s"
+#define DEV_PR_ARG  __entry->wiphy_name
+
+#define REG_ENTRY	__field(u32, reg) __field(u32, val)
+#define REG_ASSIGN	__entry->reg = reg; __entry->val = val
+#define REG_PR_FMT	" %04x=%08x"
+#define REG_PR_ARG	__entry->reg, __entry->val
+
+DECLARE_EVENT_CLASS(dev_reg_evt,
+	TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
+	TP_ARGS(dev, reg, val),
+	TP_STRUCT__entry(
+		DEV_ENTRY
+		REG_ENTRY
+	),
+	TP_fast_assign(
+		DEV_ASSIGN;
+		REG_ASSIGN;
+	),
+	TP_printk(
+		DEV_PR_FMT REG_PR_FMT,
+		DEV_PR_ARG, REG_PR_ARG
+	)
+);
+
+DEFINE_EVENT(dev_reg_evt, reg_read,
+	TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
+	TP_ARGS(dev, reg, val)
+);
+
+DEFINE_EVENT(dev_reg_evt, reg_write,
+	TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
+	TP_ARGS(dev, reg, val)
+);
+
+#endif
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE trace
+
+#include <trace/define_trace.h>
diff --git a/util.c b/util.c
index a00a71d0..f25aff9d 100644
--- a/util.c
+++ b/util.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/module.h>
 #include "mt76x2.h"
 
 void mt76_remove_hdr_pad(struct sk_buff *skb)
@@ -41,3 +42,5 @@ int mt76_insert_hdr_pad(struct sk_buff *skb)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(mt76_insert_hdr_pad);
+
+MODULE_LICENSE("GPL");