From d83d75b8b82918e686ff0ca83057d6e8f782dc57 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@openwrt.org>
Date: Sun, 13 Dec 2015 17:50:03 +0100
Subject: [PATCH] mt7603: add dma scheduler init, fixes firmware communication

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
 mt7603_init.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++
 mt7603_regs.h | 42 +++++++++++++++++++++++++++++++
 2 files changed, 110 insertions(+)

diff --git a/mt7603_init.c b/mt7603_init.c
index df705c97..5027dac0 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -99,6 +99,72 @@ int mt7603_mac_start(struct mt7603_dev *dev)
 	return 0;
 }
 
+static void
+mt7603_dma_sched_init(struct mt7603_dev *dev)
+{
+	int page_size, page_count;
+	int max_len = 1792;
+	int max_amsdu_len = 4096;
+	int max_mcu_len = 4096;
+	int max_beacon_len = 512 * 8 + max_len;
+	int max_mcast_count = 3;
+	int beacon_pages;
+	int mcu_pages;
+	int i;
+
+	page_size = mt76_get_field(dev, MT_PSE_FC_P0,
+				   MT_PSE_FC_P0_MAX_QUOTA);
+	page_count = 0x1ae;
+	beacon_pages = max_beacon_len / page_size;
+	mcu_pages = max_mcu_len / page_size;
+
+	mt76_wr(dev, MT_PSE_FRP,
+		MT76_SET(MT_PSE_FRP_P0, 7) |
+		MT76_SET(MT_PSE_FRP_P1, 6) |
+		MT76_SET(MT_PSE_FRP_P2_RQ2, 4));
+
+	mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
+	mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
+
+	mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);
+	mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);
+
+	mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);
+
+	mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));
+	mt76_wr(dev, MT_SCH_2, max_len / page_size);
+
+	for (i = 0; i <= 4; i++)
+		mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_len / page_size);
+
+	mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);
+	mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);
+
+	mt76_wr(dev, MT_PAGE_COUNT(8),
+		(max_mcast_count + 1) * max_len / page_size);
+
+	mt76_wr(dev, MT_RSV_MAX_THRESH, page_count);
+
+	if (mt76xx_rev(dev) < MT7603_REV_E2) {
+		mt76_wr(dev, MT_GROUP_THRESH(0), page_count);
+		mt76_wr(dev, MT_BMAP_0, 0xffff);
+	} else {
+		mt76_wr(dev, MT_GROUP_THRESH(0),
+			page_count - beacon_pages - mcu_pages);
+		mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);
+		mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);
+		mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);
+		mt76_wr(dev, MT_BMAP_1, 0x00000020);
+	}
+
+	mt76_wr(dev, MT_SCH_4, 0);
+
+	for (i = 0; i <= 15; i++)
+		mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);
+
+	mt76_set(dev, MT_SCH_4, BIT(6));
+}
+
 static int
 mt7603_init_hardware(struct mt7603_dev *dev)
 {
@@ -128,6 +194,8 @@ mt7603_init_hardware(struct mt7603_dev *dev)
 	if (ret)
 		return ret;
 
+	mt7603_dma_sched_init(dev);
+
 	return 0;
 }
 
diff --git a/mt7603_regs.h b/mt7603_regs.h
index b30e455d..7cace5c5 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -64,6 +64,12 @@
 #define MT_TX_RING_BASE			MT_HIF(0x300)
 #define MT_RX_RING_BASE			MT_HIF(0x400)
 
+#define MT_TXTIME_THRESH_BASE		MT_HIF(0x500)
+#define MT_TXTIME_THRESH(n)		(MT_TXTIME_THRESH_BASE + ((n) * 4))
+
+#define MT_PAGE_COUNT_BASE		MT_HIF(0x540)
+#define MT_PAGE_COUNT(n)		(MT_PAGE_COUNT_BASE + ((n) * 4))
+
 #define MT_SCH_1			MT_HIF(0x588)
 #define MT_SCH_2			MT_HIF(0x58c)
 #define MT_SCH_3			MT_HIF(0x590)
@@ -72,6 +78,37 @@
 #define MT_SCH_4_FORCE_QID		GENMASK(4, 0)
 #define MT_SCH_4_BYPASS			BIT(5)
 
+#define MT_GROUP_THRESH_BASE		MT_HIF(0x598)
+#define MT_GROUP_THRESH(n)		(MT_GROUP_THRESH_BASE + ((n) * 4))
+
+#define MT_QUEUE_PRIORITY_1		MT_HIF(0x580)
+#define MT_QUEUE_PRIORITY_2		MT_HIF(0x584)
+
+#define MT_BMAP_0			MT_HIF(0x5b0)
+#define MT_BMAP_1			MT_HIF(0x5b4)
+#define MT_BMAP_2			MT_HIF(0x5b8)
+
+#define MT_HIGH_PRIORITY_1		MT_HIF(0x5bc)
+#define MT_HIGH_PRIORITY_2		MT_HIF(0x5c0)
+
+#define MT_PRIORITY_MASK		MT_HIF(0x5c4)
+
+#define MT_RSV_MAX_THRESH		MT_HIF(0x5c8)
+
+#define MT_PSE_BASE			0x8000
+#define MT_PSE(ofs)			(MT_PSE_BASE + (ofs))
+
+#define MT_PSE_FC_P0			MT_PSE(0x120)
+#define MT_PSE_FC_P0_MIN_RESERVE	GENMASK(11, 0)
+#define MT_PSE_FC_P0_MAX_QUOTA		GENMASK(27, 16)
+
+#define MT_PSE_FRP			MT_PSE(0x138)
+#define MT_PSE_FRP_P0			GENMASK(2, 0)
+#define MT_PSE_FRP_P1			GENMASK(5, 3)
+#define MT_PSE_FRP_P2_RQ0		GENMASK(8, 6)
+#define MT_PSE_FRP_P2_RQ1		GENMASK(11, 9)
+#define MT_PSE_FRP_P2_RQ2		GENMASK(14, 12)
+
 #define MT_WF_AGG_BASE			0x21200
 #define MT_WF_AGG(ofs)			(MT_WF_AGG_BASE + (ofs))
 
@@ -143,4 +180,9 @@
 
 #define MT_TMAC_INFO_TEMPLATE		0x800c0040
 
+#define MT_PSE_BASE_PHYS_ADDR		0xa0000000
+
+#define MT_PSE_WTBL_2_PHYS_ADDR		0xa5000000
+
+
 #endif