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wifi: mt76: mt792x: add MT7927 WFSYS reset support

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Add a dedicated MT7927 WFSYS reset path in mt792x_wfsys_reset().

Unlike the existing connac2/connac3 reset flow that toggles the WFSYS
software reset bit and waits for init-done, MT7927 reset is driven
through CBInfra and requires polling ROMCODE_INDEX until the MCU returns
to the idle value after reset.

Keep this dormant for now: no MT7927 PCI IDs are added by this patch, so
it only prepares the reset logic without making the driver bind to MT7927
hardware yet.

Signed-off-by: Sean Wang <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Sean Wang
2026-05-28 13:32:33 +02:00
committed by Felix Fietkau
parent 3969bb1171
commit d045c72b29
2 changed files with 67 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
mt792x_dma.c
+56 -1
View File
@@ -370,7 +370,54 @@ int mt792x_poll_rx(struct napi_struct *napi, int budget)
} }
EXPORT_SYMBOL_GPL(mt792x_poll_rx); EXPORT_SYMBOL_GPL(mt792x_poll_rx);
int mt792x_wfsys_reset(struct mt792x_dev *dev) static void mt7927_sema_status_read(struct mt792x_dev *dev, u32 addr)
{
u32 remap;
remap = mt76_rr(dev, MT7927_PCIE2AP_REMAP_WF_0_54);
mt76_wr(dev, MT7927_PCIE2AP_REMAP_WF_0_54,
(remap & ~MT7927_PCIE2AP_REMAP_WF_0_54_MASK) |
MT7927_PCIE2AP_REMAP_WF_0_54_VAL);
usleep_range(10, 20);
mt76_rr(dev, addr);
mt76_wr(dev, MT7927_PCIE2AP_REMAP_WF_0_54, remap);
usleep_range(10, 20);
}
static int mt7927_wfsys_reset(struct mt792x_dev *dev)
{
struct mt76_dev *mdev = &dev->mt76;
u32 val;
mt7927_sema_status_read(dev, MT7927_SEMA_OWN_STA);
mt76_set(dev, MT7927_CBINFRA_RGU_WF_RST,
MT7927_CBINFRA_RGU_WF_RST_WF_SUBSYS);
usleep_range(1000, 2000);
mt76_clear(dev, MT7927_CBINFRA_RGU_WF_RST,
MT7927_CBINFRA_RGU_WF_RST_WF_SUBSYS);
usleep_range(5000, 10000);
mt76_wr(dev, MT7927_CBINFRA_MCU_OWN_SET, BIT(0));
if (!__mt76_poll_msec(mdev, MT7927_ROMCODE_INDEX, 0xffff,
MT7927_MCU_IDLE_VALUE, 200)) {
val = mt76_rr(dev, MT7927_ROMCODE_INDEX);
dev_err(mdev->dev,
"MT7927 WFSYS reset timeout (ROMCODE_INDEX=0x%04x)\n",
val & 0xffff);
return -ETIMEDOUT;
}
mt7927_sema_status_read(dev, MT7927_SEMA_OWN_STA_REP);
return 0;
}
static int mt792x_wfsys_reset_default(struct mt792x_dev *dev)
{ {
u32 addr = is_connac2(&dev->mt76) ? 0x18000140 : 0x7c000140; u32 addr = is_connac2(&dev->mt76) ? 0x18000140 : 0x7c000140;
@@ -384,5 +431,13 @@ int mt792x_wfsys_reset(struct mt792x_dev *dev)
return 0; return 0;
} }
int mt792x_wfsys_reset(struct mt792x_dev *dev)
{
if (is_mt7927(&dev->mt76))
return mt7927_wfsys_reset(dev);
return mt792x_wfsys_reset_default(dev);
}
EXPORT_SYMBOL_GPL(mt792x_wfsys_reset); EXPORT_SYMBOL_GPL(mt792x_wfsys_reset);
mt792x_regs.h
+11
View File
@@ -493,4 +493,15 @@
#define WFSYS_SW_RST_B BIT(0) #define WFSYS_SW_RST_B BIT(0)
#define WFSYS_SW_INIT_DONE BIT(4) #define WFSYS_SW_INIT_DONE BIT(4)
/* CBInfra registers - MT7927 combo chip */
#define MT7927_CBINFRA_RGU_WF_RST 0x1f8600
#define MT7927_CBINFRA_RGU_WF_RST_WF_SUBSYS BIT(4)
#define MT7927_CBINFRA_MCU_OWN_SET 0x1f5034
#define MT7927_ROMCODE_INDEX 0xc1604
#define MT7927_MCU_IDLE_VALUE 0x1d1e
#define MT7927_PCIE2AP_REMAP_WF_0_54 0x21008
#define MT7927_PCIE2AP_REMAP_WF_0_54_MASK GENMASK(15, 0)
#define MT7927_PCIE2AP_REMAP_WF_0_54_VAL 0x00001807
#define MT7927_SEMA_OWN_STA 0x40000
#define MT7927_SEMA_OWN_STA_REP 0x40400
#endif /* __MT792X_REGS_H */ #endif /* __MT792X_REGS_H */