mirror of
https://github.com/outbackdingo/mt76.git
synced 2026-10-24 13:26:48 +00:00
use the new bitfield accessor macros
Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
@@ -66,10 +66,10 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
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for (i = 0; i < nbufs; i += 2, buf += 2) {
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u32 buf0 = buf[0].addr, buf1 = 0;
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ctrl = MT76_SET(MT_DMA_CTL_SD_LEN0, buf[0].len);
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ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
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if (i < nbufs - 1) {
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buf1 = buf[1].addr;
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ctrl |= MT76_SET(MT_DMA_CTL_SD_LEN1, buf[1].len);
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ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
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}
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if (i == nbufs - 1)
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@@ -106,14 +106,14 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
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if (!e->txwi || !e->skb) {
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__le32 addr = ACCESS_ONCE(q->desc[idx].buf0);
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u32 len = MT76_GET(MT_DMA_CTL_SD_LEN0, ctrl);
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u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
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dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
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DMA_TO_DEVICE);
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}
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if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) {
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__le32 addr = ACCESS_ONCE(q->desc[idx].buf1);
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u32 len = MT76_GET(MT_DMA_CTL_SD_LEN1, ctrl);
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u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl);
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dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
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DMA_TO_DEVICE);
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}
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@@ -194,7 +194,7 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
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buf_addr = ACCESS_ONCE(desc->buf0);
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if (len) {
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u32 ctl = ACCESS_ONCE(desc->ctrl);
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*len = MT76_GET(MT_DMA_CTL_SD_LEN0, ctl);
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*len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
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*more = !(ctl & MT_DMA_CTL_LAST_SEC0);
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}
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@@ -251,10 +251,10 @@ struct mt76_rate_power {
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#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
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#define mt76_get_field(_dev, _reg, _field) \
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MT76_GET(_field, mt76_rr(dev, _reg))
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FIELD_GET(_field, mt76_rr(dev, _reg))
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#define mt76_rmw_field(_dev, _reg, _field, _val) \
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mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
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mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
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#define mt76_hw(dev) (dev)->mt76.hw
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+1
-1
@@ -158,7 +158,7 @@ void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval)
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dev->beacon_int = intval;
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mt76_wr(dev, MT_TBTT,
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MT76_SET(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
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FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
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mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */
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+1
-1
@@ -68,7 +68,7 @@ void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
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__le32 *end = (__le32 *) &skb->data[skb->len];
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enum rx_pkt_type type;
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type = MT76_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
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type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
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switch(type) {
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case PKT_TYPE_TXS:
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+1
-1
@@ -26,7 +26,7 @@ mt7603_efuse_read(struct mt7603_dev *dev, u32 base, u16 addr, u8 *data)
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val = mt76_rr(dev, base + MT_EFUSE_CTRL);
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val &= ~(MT_EFUSE_CTRL_AIN |
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MT_EFUSE_CTRL_MODE);
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val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf);
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val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
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val |= MT_EFUSE_CTRL_KICK;
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mt76_wr(dev, base + MT_EFUSE_CTRL, val);
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+28
-28
@@ -47,7 +47,7 @@ static void
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mt7603_set_tmac_template(struct mt7603_dev *dev)
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{
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u32 desc[5] = {
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[1] = MT76_SET(MT_TXD3_REM_TX_COUNT, 0xf),
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[1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
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[3] = MT_TXD5_SW_POWER_MGMT
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};
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u32 addr;
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@@ -79,9 +79,9 @@ mt7603_dma_sched_init(struct mt7603_dev *dev)
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mcu_pages = max_mcu_len / page_size;
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mt76_wr(dev, MT_PSE_FRP,
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MT76_SET(MT_PSE_FRP_P0, 7) |
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MT76_SET(MT_PSE_FRP_P1, 6) |
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MT76_SET(MT_PSE_FRP_P2_RQ2, 4));
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FIELD_PREP(MT_PSE_FRP_P0, 7) |
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FIELD_PREP(MT_PSE_FRP_P1, 6) |
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FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));
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mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
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mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
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@@ -134,8 +134,8 @@ mt7603_phy_init(struct mt7603_dev *dev)
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mt76_rmw(dev, MT_WF_RMAC_RMCR,
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(MT_WF_RMAC_RMCR_SMPS_MODE |
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MT_WF_RMAC_RMCR_RX_STREAMS),
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(MT76_SET(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
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MT76_SET(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
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(FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
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FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
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mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
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tx_chains);
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@@ -161,25 +161,25 @@ mt7603_mac_init(struct mt7603_dev *dev)
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(MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
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mt76_wr(dev, MT_AGG_LIMIT,
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MT76_SET(MT_AGG_LIMIT_AC(0), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(1), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(2), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(3), 21));
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FIELD_PREP(MT_AGG_LIMIT_AC(0), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(1), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(2), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(3), 21));
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mt76_wr(dev, MT_AGG_LIMIT_1,
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MT76_SET(MT_AGG_LIMIT_AC(0), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(1), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(2), 21) |
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MT76_SET(MT_AGG_LIMIT_AC(3), 21));
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FIELD_PREP(MT_AGG_LIMIT_AC(0), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(1), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(2), 21) |
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FIELD_PREP(MT_AGG_LIMIT_AC(3), 21));
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mt76_wr(dev, MT_AGG_CONTROL,
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MT76_SET(MT_AGG_CONTROL_BAR_RATE, 0x80) |
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MT76_SET(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
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FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x80) |
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FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
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MT_AGG_CONTROL_NO_BA_AR_RULE);
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mt76_wr(dev, MT_AGG_RETRY_CONTROL,
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MT76_SET(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
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MT76_SET(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
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FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
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FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
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mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, MT_RX_BUF_SIZE);
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@@ -213,7 +213,7 @@ mt7603_mac_init(struct mt7603_dev *dev)
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/* Configure txs selection with aggregation */
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mt76_wr(dev, MT_DMA_TCFR1,
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MT76_SET(MT_DMA_TCFR1_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
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FIELD_PREP(MT_DMA_TCFR1_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
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MT_DMA_TCFR1_TXS_AGGR_COUNT | /* Maximum count */
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MT_DMA_TCFR1_TXS_QUEUE | /* Queue 1 */
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MT_DMA_TCFR1_TXS_BIT_MAP);
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@@ -234,17 +234,17 @@ mt7603_mac_init(struct mt7603_dev *dev)
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mt76_wr(dev, MT_AGG_ARUCR, 0);
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mt76_wr(dev, MT_AGG_ARDCR,
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MT76_SET(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
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MT76_SET(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
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FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
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mt76_wr(dev, MT_AGG_ARCR, (MT_AGG_ARCR_INIT_RATE1 |
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MT76_SET(MT_AGG_ARCR_RTS_RATE_THR, 2)));
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FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2)));
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mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);
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+67
-67
@@ -46,13 +46,13 @@ mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
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void mt7603_mac_set_timing(struct mt7603_dev *dev)
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{
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u32 cck = MT76_SET(MT_TIMEOUT_VAL_PLCP, 247) |
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MT76_SET(MT_TIMEOUT_VAL_CCA, 64);
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u32 ofdm = MT76_SET(MT_TIMEOUT_VAL_PLCP, 113) |
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MT76_SET(MT_TIMEOUT_VAL_CCA, 64);
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u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 247) |
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 64);
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u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 113) |
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, 64);
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int offset = 3 * dev->coverage_class;
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u32 reg_offset = MT76_SET(MT_TIMEOUT_VAL_PLCP, offset) |
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MT76_SET(MT_TIMEOUT_VAL_CCA, offset);
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u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
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FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
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int sifs;
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if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
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@@ -69,7 +69,7 @@ static void
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mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
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{
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mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
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MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
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FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
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mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
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}
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@@ -108,9 +108,9 @@ void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, const u8 *mac_addr)
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int i;
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mt76_set(dev, addr + 0 * 4,
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MT76_SET(MT_WTBL1_W0_ADDR_HI, get_unaligned_le16(_mac + 4)));
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FIELD_PREP(MT_WTBL1_W0_ADDR_HI, get_unaligned_le16(_mac + 4)));
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mt76_set(dev, addr + 1 * 4,
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MT76_SET(MT_WTBL1_W1_ADDR_LO, get_unaligned_le32(_mac)));
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FIELD_PREP(MT_WTBL1_W1_ADDR_LO, get_unaligned_le32(_mac)));
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mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
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addr = mt7603_wtbl2_addr(idx);
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@@ -166,14 +166,14 @@ void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
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mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
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mt76_wr(dev, addr + 3 * 4,
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MT76_SET(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
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MT76_SET(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
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MT76_SET(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
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FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
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FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
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FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
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MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
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mt76_wr(dev, addr + 4 * 4,
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MT76_SET(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
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MT76_SET(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
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MT76_SET(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
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FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
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FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
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FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
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mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
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@@ -204,8 +204,8 @@ void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
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val = mt76_rr(dev, addr + 2 * 4);
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val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
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val |= MT76_SET(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) |
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MT76_SET(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) |
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val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) |
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FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) |
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MT_WTBL1_W2_TXS_BAF_REPORT;
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if (sta->ht_cap.cap)
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@@ -231,7 +231,7 @@ void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
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mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
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mt76_wr(dev, MT_BA_CONTROL_1,
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(get_unaligned_le16(addr + 4) |
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MT76_SET(MT_BA_CONTROL_1_TID, tid) |
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FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
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MT_BA_CONTROL_1_RESET));
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}
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@@ -239,7 +239,7 @@ void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, int ssn,
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int ba_size)
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{
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u32 addr = mt7603_wtbl2_addr(wcid);
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u32 tid_mask = MT76_SET(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
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u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
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(MT_WTBL2_W15_BA_WIN_SIZE <<
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(tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
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u32 tid_val;
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@@ -293,7 +293,7 @@ void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, int ssn,
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break;
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}
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tid_val = MT76_SET(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
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tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
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i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
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mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
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@@ -337,7 +337,7 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
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memset(status, 0, sizeof(*status));
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i = MT76_GET(MT_RXD1_NORMAL_CH_FREQ, rxd[1]);
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i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd[1]);
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sband = (i & 1) ? &dev->mt76.sband_5g.sband : &dev->mt76.sband_2g.sband;
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i >>= 1;
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@@ -351,7 +351,7 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
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if (rxd[2] & MT_RXD2_NORMAL_TKIP_MIC_ERR)
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status->flag |= RX_FLAG_MMIC_ERROR;
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if (MT76_GET(MT_RXD2_NORMAL_SEC_MODE, rxd[2]) != 0 &&
|
||||
if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd[2]) != 0 &&
|
||||
!(rxd[2] & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
|
||||
status->flag |= RX_FLAG_DECRYPTED;
|
||||
status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED;
|
||||
@@ -384,8 +384,8 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
|
||||
if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
|
||||
bool cck = false;
|
||||
|
||||
i = MT76_GET(MT_RXV1_TX_RATE, rxd[0]);
|
||||
switch (MT76_GET(MT_RXV1_TX_MODE, rxd[0])) {
|
||||
i = FIELD_GET(MT_RXV1_TX_RATE, rxd[0]);
|
||||
switch (FIELD_GET(MT_RXV1_TX_MODE, rxd[0])) {
|
||||
case MT_PHY_TYPE_CCK:
|
||||
cck = true;
|
||||
/* fall through */
|
||||
@@ -407,14 +407,14 @@ mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
|
||||
status->flag |= RX_FLAG_SHORT_GI;
|
||||
|
||||
status->flag |= RX_FLAG_STBC_MASK *
|
||||
MT76_GET(MT_RXV1_HT_STBC, rxd[0]);
|
||||
FIELD_GET(MT_RXV1_HT_STBC, rxd[0]);
|
||||
|
||||
status->rate_idx = i;
|
||||
|
||||
status->chains = BIT(0) | BIT(1);
|
||||
status->chain_signal[0] = MT76_GET(MT_RXV4_IB_RSSI0, rxd[3]) +
|
||||
status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxd[3]) +
|
||||
dev->rssi_offset[0];
|
||||
status->chain_signal[1] = MT76_GET(MT_RXV4_IB_RSSI1, rxd[3]) +
|
||||
status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxd[3]) +
|
||||
dev->rssi_offset[1];
|
||||
status->signal = max(status->chain_signal[0], status->chain_signal[1]);
|
||||
|
||||
@@ -460,8 +460,8 @@ mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
|
||||
rate_idx = val & 0xff;
|
||||
}
|
||||
|
||||
rateval = (MT76_SET(MT_TX_RATE_IDX, rate_idx) |
|
||||
MT76_SET(MT_TX_RATE_MODE, phy));
|
||||
rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
|
||||
FIELD_PREP(MT_TX_RATE_MODE, phy));
|
||||
|
||||
if (stbc && nss == 1)
|
||||
rateval |= MT_TX_RATE_STBC;
|
||||
@@ -494,8 +494,8 @@ void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta)
|
||||
MT_WTBL2_W9_SHORT_GI_80;
|
||||
|
||||
val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
|
||||
w9 |= MT76_SET(MT_WTBL2_W9_CC_BW_SEL, bw);
|
||||
w9 |= MT76_SET(MT_WTBL2_W9_BW_CAP, bw);
|
||||
w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
|
||||
w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
|
||||
|
||||
bw_prev = bw;
|
||||
val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
|
||||
@@ -512,29 +512,29 @@ void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta)
|
||||
if (bw_prev < bw && !bw_idx)
|
||||
bw_idx = 3;
|
||||
|
||||
w9 |= MT76_SET(MT_WTBL2_W9_CHANGE_BW_RATE,
|
||||
w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
|
||||
bw_idx ? bw_idx - 1 : 7);
|
||||
|
||||
mt76_wr(dev, MT_WTBL_RIUCR0, w9);
|
||||
|
||||
mt76_wr(dev, MT_WTBL_RIUCR1,
|
||||
MT76_SET(MT_WTBL_RIUCR1_RATE0, val[0]) |
|
||||
MT76_SET(MT_WTBL_RIUCR1_RATE1, val[0]) |
|
||||
MT76_SET(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
|
||||
FIELD_PREP(MT_WTBL_RIUCR1_RATE0, val[0]) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
|
||||
|
||||
mt76_wr(dev, MT_WTBL_RIUCR2,
|
||||
MT76_SET(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
|
||||
MT76_SET(MT_WTBL_RIUCR2_RATE3, val[1]) |
|
||||
MT76_SET(MT_WTBL_RIUCR2_RATE4, val[2]) |
|
||||
MT76_SET(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
|
||||
FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
|
||||
|
||||
mt76_wr(dev, MT_WTBL_RIUCR3,
|
||||
MT76_SET(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
|
||||
MT76_SET(MT_WTBL_RIUCR3_RATE6, val[3]) |
|
||||
MT76_SET(MT_WTBL_RIUCR3_RATE7, val[3]));
|
||||
FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
|
||||
FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
|
||||
|
||||
mt76_wr(dev, MT_WTBL_UPDATE,
|
||||
MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
|
||||
FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
|
||||
MT_WTBL_UPDATE_RATE_UPDATE |
|
||||
MT_WTBL_UPDATE_TX_COUNT_CLEAR);
|
||||
|
||||
@@ -624,24 +624,24 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
else
|
||||
wlan_idx = MT7603_WTBL_RESERVED;
|
||||
|
||||
frame_type = MT76_GET(IEEE80211_FCTL_FTYPE,
|
||||
frame_type = FIELD_GET(IEEE80211_FCTL_FTYPE,
|
||||
le16_to_cpu(hdr->frame_control));
|
||||
frame_subtype = MT76_GET(IEEE80211_FCTL_STYPE,
|
||||
frame_subtype = FIELD_GET(IEEE80211_FCTL_STYPE,
|
||||
le16_to_cpu(hdr->frame_control));
|
||||
|
||||
txwi[0] = cpu_to_le32(
|
||||
MT76_SET(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
|
||||
MT76_SET(MT_TXD0_Q_IDX, q->hw_idx)
|
||||
FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
|
||||
FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx)
|
||||
);
|
||||
txwi[1] = cpu_to_le32(
|
||||
MT_TXD1_LONG_FORMAT |
|
||||
MT76_SET(MT_TXD1_OWN_MAC, 0) |
|
||||
MT76_SET(MT_TXD1_TID, skb->priority &
|
||||
FIELD_PREP(MT_TXD1_OWN_MAC, 0) |
|
||||
FIELD_PREP(MT_TXD1_TID, skb->priority &
|
||||
IEEE80211_QOS_CTL_TID_MASK) |
|
||||
MT76_SET(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
|
||||
MT76_SET(MT_TXD1_HDR_INFO, hdr_len / 2) |
|
||||
MT76_SET(MT_TXD1_WLAN_IDX, wlan_idx) |
|
||||
MT76_SET(MT_TXD1_PROTECTED, !!key)
|
||||
FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
|
||||
FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
|
||||
FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
|
||||
FIELD_PREP(MT_TXD1_PROTECTED, !!key)
|
||||
);
|
||||
|
||||
if (info->flags & IEEE80211_TX_CTL_NO_ACK) {
|
||||
@@ -650,9 +650,9 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
}
|
||||
|
||||
txwi[2] = cpu_to_le32(
|
||||
MT76_SET(MT_TXD2_FRAME_TYPE, frame_type) |
|
||||
MT76_SET(MT_TXD2_SUB_TYPE, frame_subtype) |
|
||||
MT76_SET(MT_TXD2_MULTICAST, is_multicast_ether_addr(hdr->addr1))
|
||||
FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
|
||||
FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
|
||||
FIELD_PREP(MT_TXD2_MULTICAST, is_multicast_ether_addr(hdr->addr1))
|
||||
);
|
||||
|
||||
if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
|
||||
@@ -661,7 +661,7 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
txwi[4] = 0;
|
||||
txwi[5] = cpu_to_le32(
|
||||
MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
|
||||
MT76_SET(MT_TXD5_PID, pid)
|
||||
FIELD_PREP(MT_TXD5_PID, pid)
|
||||
);
|
||||
txwi[6] = 0;
|
||||
|
||||
@@ -672,8 +672,8 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
txwi[6] |= cpu_to_le32(
|
||||
MT_TXD6_FIXED_RATE |
|
||||
MT_TXD6_FIXED_BW |
|
||||
MT76_SET(MT_TXD6_BW, bw) |
|
||||
MT76_SET(MT_TXD6_TX_RATE, rateval)
|
||||
FIELD_PREP(MT_TXD6_BW, bw) |
|
||||
FIELD_PREP(MT_TXD6_TX_RATE, rateval)
|
||||
);
|
||||
|
||||
if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
|
||||
@@ -690,15 +690,15 @@ mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
|
||||
tx_count = 0x1f;
|
||||
|
||||
txwi[3] = cpu_to_le32(
|
||||
MT76_SET(MT_TXD3_REM_TX_COUNT, tx_count) |
|
||||
MT76_SET(MT_TXD3_SEQ, le16_to_cpu(hdr->seq_ctrl))
|
||||
FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
|
||||
FIELD_PREP(MT_TXD3_SEQ, le16_to_cpu(hdr->seq_ctrl))
|
||||
);
|
||||
|
||||
if (key) {
|
||||
u64 pn = atomic64_inc_return(&key->tx_pn);
|
||||
txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
|
||||
txwi[4] = pn & GENMASK(31, 0);
|
||||
txwi[5] |= MT76_SET(MT_TXD5_PN_HIGH, pn >> 32);
|
||||
txwi[5] |= FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32);
|
||||
}
|
||||
|
||||
txwi[7] = 0;
|
||||
@@ -784,8 +784,8 @@ mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
|
||||
txs = le32_to_cpu(txs_data[4]);
|
||||
final_mpdu = txs & MT_TXS4_ACKED_MPDU;
|
||||
ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
|
||||
pid = MT76_GET(MT_TXS4_PID, txs);
|
||||
count = MT76_GET(MT_TXS4_TX_COUNT, txs);
|
||||
pid = FIELD_GET(MT_TXS4_PID, txs);
|
||||
count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
|
||||
|
||||
txs = le32_to_cpu(txs_data[0]);
|
||||
ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
|
||||
@@ -917,9 +917,9 @@ void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
|
||||
u8 pid;
|
||||
|
||||
txs = le32_to_cpu(txs_data[4]);
|
||||
pid = MT76_GET(MT_TXS4_PID, txs);
|
||||
pid = FIELD_GET(MT_TXS4_PID, txs);
|
||||
txs = le32_to_cpu(txs_data[3]);
|
||||
wcidx = MT76_GET(MT_TXS3_WCID, txs);
|
||||
wcidx = FIELD_GET(MT_TXS3_WCID, txs);
|
||||
|
||||
if (pid == MT_PID_NOACK)
|
||||
return;
|
||||
@@ -1026,7 +1026,7 @@ void mt7603_mac_dma_start(struct mt7603_dev *dev)
|
||||
mt76_set(dev, MT_WPDMA_GLO_CFG,
|
||||
(MT_WPDMA_GLO_CFG_TX_DMA_EN |
|
||||
MT_WPDMA_GLO_CFG_RX_DMA_EN |
|
||||
MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
|
||||
FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
|
||||
MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
|
||||
|
||||
mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
|
||||
|
||||
+1
-1
@@ -248,7 +248,7 @@ mt7603_load_firmware(struct mt7603_dev *dev)
|
||||
|
||||
/* switch to bypass mode */
|
||||
mt76_rmw(dev, MT_SCH_4, MT_SCH_4_FORCE_QID,
|
||||
MT_SCH_4_BYPASS | MT76_SET(MT_SCH_4_FORCE_QID, 5));
|
||||
MT_SCH_4_BYPASS | FIELD_PREP(MT_SCH_4_FORCE_QID, 5));
|
||||
|
||||
val = mt76_rr(dev, MT_TOP_MISC2);
|
||||
if (val & BIT(1)) {
|
||||
|
||||
+4
-4
@@ -28,10 +28,10 @@ mt76x2_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76_txq_id qid,
|
||||
int idx;
|
||||
|
||||
tx_info = MT_MCU_MSG_TYPE_CMD |
|
||||
MT76_SET(MT_MCU_MSG_CMD_TYPE, cmd) |
|
||||
MT76_SET(MT_MCU_MSG_CMD_SEQ, seq) |
|
||||
MT76_SET(MT_MCU_MSG_PORT, CPU_TX_PORT) |
|
||||
MT76_SET(MT_MCU_MSG_LEN, skb->len);
|
||||
FIELD_PREP(MT_MCU_MSG_CMD_TYPE, cmd) |
|
||||
FIELD_PREP(MT_MCU_MSG_CMD_SEQ, seq) |
|
||||
FIELD_PREP(MT_MCU_MSG_PORT, CPU_TX_PORT) |
|
||||
FIELD_PREP(MT_MCU_MSG_LEN, skb->len);
|
||||
|
||||
addr = dma_map_single(dev->mt76.dev, skb->data, skb->len, DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(dev->mt76.dev, addr))
|
||||
|
||||
+2
-2
@@ -45,7 +45,7 @@ mt76x2_eeprom_parse_hw_cap(struct mt76x2_dev *dev)
|
||||
{
|
||||
u16 val = MT_EE_NIC_CONF_0;
|
||||
|
||||
switch (MT76_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) {
|
||||
switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) {
|
||||
case BOARD_TYPE_5GHZ:
|
||||
dev->mt76.cap.has_5ghz = true;
|
||||
break;
|
||||
@@ -68,7 +68,7 @@ mt76x2_efuse_read(struct mt76x2_dev *dev, u16 addr, u8 *data)
|
||||
val = mt76_rr(dev, MT_EFUSE_CTRL);
|
||||
val &= ~(MT_EFUSE_CTRL_AIN |
|
||||
MT_EFUSE_CTRL_MODE);
|
||||
val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf);
|
||||
val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
|
||||
val |= MT_EFUSE_CTRL_KICK;
|
||||
mt76_wr(dev, MT_EFUSE_CTRL, val);
|
||||
|
||||
|
||||
+15
-15
@@ -85,22 +85,22 @@ static void
|
||||
mt76_write_mac_initvals(struct mt76x2_dev *dev)
|
||||
{
|
||||
#define DEFAULT_PROT_CFG \
|
||||
(MT76_SET(MT_PROT_CFG_RATE, 0x2004) | \
|
||||
MT76_SET(MT_PROT_CFG_NAV, 1) | \
|
||||
MT76_SET(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
|
||||
(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
|
||||
FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
|
||||
FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
|
||||
MT_PROT_CFG_RTS_THRESH)
|
||||
|
||||
#define DEFAULT_PROT_CFG_20 \
|
||||
(MT76_SET(MT_PROT_CFG_RATE, 0x2004) | \
|
||||
MT76_SET(MT_PROT_CFG_CTRL, 1) | \
|
||||
MT76_SET(MT_PROT_CFG_NAV, 1) | \
|
||||
MT76_SET(MT_PROT_CFG_TXOP_ALLOW, 0x17))
|
||||
(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
|
||||
FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
|
||||
FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
|
||||
FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
|
||||
|
||||
#define DEFAULT_PROT_CFG_40 \
|
||||
(MT76_SET(MT_PROT_CFG_RATE, 0x2084) | \
|
||||
MT76_SET(MT_PROT_CFG_CTRL, 1) | \
|
||||
MT76_SET(MT_PROT_CFG_NAV, 1) | \
|
||||
MT76_SET(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
|
||||
(FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
|
||||
FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
|
||||
FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
|
||||
FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
|
||||
|
||||
static const struct mt76x2_reg_pair vals[] = {
|
||||
/* Copied from MediaTek reference source */
|
||||
@@ -199,7 +199,7 @@ mt76x2_fixup_xtal(struct mt76x2_dev *dev)
|
||||
mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
|
||||
|
||||
eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
|
||||
switch (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
|
||||
switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
|
||||
case 0:
|
||||
mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
|
||||
break;
|
||||
@@ -245,7 +245,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
|
||||
MT_WPDMA_GLO_CFG_RX_DMA_EN |
|
||||
MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
|
||||
MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
|
||||
val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
|
||||
val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
|
||||
|
||||
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
|
||||
|
||||
@@ -276,7 +276,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
|
||||
|
||||
mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr));
|
||||
mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) |
|
||||
MT76_SET(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
|
||||
FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
|
||||
MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
|
||||
|
||||
/* Fire a pre-TBTT interrupt 8 ms before TBTT */
|
||||
@@ -311,7 +311,7 @@ int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
|
||||
MT_CH_TIME_CFG_RX_AS_BUSY |
|
||||
MT_CH_TIME_CFG_NAV_AS_BUSY |
|
||||
MT_CH_TIME_CFG_EIFS_AS_BUSY |
|
||||
MT76_SET(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
|
||||
FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
|
||||
|
||||
mt76x2_init_beacon_offsets(dev);
|
||||
|
||||
|
||||
+22
-22
@@ -31,9 +31,9 @@ void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr)
|
||||
static void
|
||||
mt76x2_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
|
||||
{
|
||||
u8 idx = MT76_GET(MT_RXWI_RATE_INDEX, rate);
|
||||
u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
|
||||
|
||||
switch (MT76_GET(MT_RXWI_RATE_PHY, rate)) {
|
||||
switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
|
||||
case MT_PHY_TYPE_OFDM:
|
||||
if (idx >= 8)
|
||||
idx = 0;
|
||||
@@ -63,8 +63,8 @@ mt76x2_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
|
||||
break;
|
||||
case MT_PHY_TYPE_VHT:
|
||||
status->flag |= RX_FLAG_VHT;
|
||||
status->rate_idx = MT76_GET(MT_RATE_INDEX_VHT_IDX, idx);
|
||||
status->vht_nss = MT76_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1;
|
||||
status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx);
|
||||
status->vht_nss = FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1;
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
@@ -80,7 +80,7 @@ mt76x2_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
|
||||
if (rate & MT_RXWI_RATE_STBC)
|
||||
status->flag |= 1 << RX_FLAG_STBC_SHIFT;
|
||||
|
||||
switch (MT76_GET(MT_RXWI_RATE_BW, rate)) {
|
||||
switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
|
||||
case MT_PHY_BW_20:
|
||||
break;
|
||||
case MT_PHY_BW_40:
|
||||
@@ -135,9 +135,9 @@ mt76x2_mac_tx_rate_val(struct mt76x2_dev *dev, const struct ieee80211_tx_rate *r
|
||||
bw = 0;
|
||||
}
|
||||
|
||||
rateval = MT76_SET(MT_RXWI_RATE_INDEX, rate_idx);
|
||||
rateval |= MT76_SET(MT_RXWI_RATE_PHY, phy);
|
||||
rateval |= MT76_SET(MT_RXWI_RATE_BW, bw);
|
||||
rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
|
||||
rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
|
||||
rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
|
||||
if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
|
||||
rateval |= MT_RXWI_RATE_SGI;
|
||||
|
||||
@@ -160,7 +160,7 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
{
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||
struct ieee80211_tx_rate *rate = &info->control.rates[0];
|
||||
u16 rate_ht_mask = MT76_SET(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
|
||||
u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
|
||||
u16 txwi_flags = 0;
|
||||
u8 nss;
|
||||
s8 txpwr_adj, max_txpwr_adj;
|
||||
@@ -187,7 +187,7 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
|
||||
txpwr_adj = mt76x2_tx_get_txpwr_adj(dev, dev->txpower_conf,
|
||||
max_txpwr_adj);
|
||||
txwi->ctl2 = MT76_SET(MT_TX_PWR_ADJ, txpwr_adj);
|
||||
txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
|
||||
|
||||
if (mt76xx_rev(dev) >= MT76XX_REV_E4)
|
||||
txwi->txstream = 0x13;
|
||||
@@ -213,10 +213,10 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
|
||||
ba_size = min_t(int, 63, ba_size - 1);
|
||||
if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
|
||||
ba_size = 0;
|
||||
txwi->ack_ctl |= MT76_SET(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
|
||||
txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
|
||||
|
||||
txwi_flags |= MT_TXWI_FLAGS_AMPDU |
|
||||
MT76_SET(MT_TXWI_FLAGS_MPDU_DENSITY,
|
||||
FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
|
||||
sta->ht_cap.ampdu_density);
|
||||
}
|
||||
|
||||
@@ -240,7 +240,7 @@ int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb, void *rxi
|
||||
status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED;
|
||||
}
|
||||
|
||||
len = MT76_GET(MT_RXWI_CTL_MPDU_LEN, ctl);
|
||||
len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl);
|
||||
if (WARN_ON_ONCE(len > skb->len))
|
||||
return -EINVAL;
|
||||
|
||||
@@ -261,13 +261,13 @@ static void
|
||||
mt76x2_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
|
||||
enum nl80211_band band)
|
||||
{
|
||||
u8 idx = MT76_GET(MT_RXWI_RATE_INDEX, rate);
|
||||
u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
|
||||
|
||||
txrate->idx = 0;
|
||||
txrate->flags = 0;
|
||||
txrate->count = 1;
|
||||
|
||||
switch (MT76_GET(MT_RXWI_RATE_PHY, rate)) {
|
||||
switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
|
||||
case MT_PHY_TYPE_OFDM:
|
||||
if (band == NL80211_BAND_2GHZ)
|
||||
idx += 4;
|
||||
@@ -296,7 +296,7 @@ mt76x2_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
|
||||
return;
|
||||
}
|
||||
|
||||
switch (MT76_GET(MT_RXWI_RATE_BW, rate)) {
|
||||
switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
|
||||
case MT_PHY_BW_20:
|
||||
break;
|
||||
case MT_PHY_BW_40:
|
||||
@@ -436,10 +436,10 @@ void mt76x2_mac_poll_tx_status(struct mt76x2_dev *dev, bool irq)
|
||||
stat.success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS);
|
||||
stat.aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR);
|
||||
stat.ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ);
|
||||
stat.wcid = MT76_GET(MT_TX_STAT_FIFO_WCID, stat1);
|
||||
stat.rate = MT76_GET(MT_TX_STAT_FIFO_RATE, stat1);
|
||||
stat.retry = MT76_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2);
|
||||
stat.pktid = MT76_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2);
|
||||
stat.wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1);
|
||||
stat.rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1);
|
||||
stat.retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2);
|
||||
stat.pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2);
|
||||
trace_mac_txstat_fetch(dev, &stat);
|
||||
|
||||
if (!irq) {
|
||||
@@ -520,8 +520,8 @@ void mt76x2_mac_wcid_setup(struct mt76x2_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
|
||||
struct mt76_wcid_addr addr = {};
|
||||
u32 attr;
|
||||
|
||||
attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
|
||||
MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
|
||||
attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
|
||||
FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
|
||||
|
||||
mt76_wr(dev, MT_WCID_ATTR(idx), attr);
|
||||
|
||||
|
||||
+4
-4
@@ -356,10 +356,10 @@ mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
|
||||
if (params->cw_max)
|
||||
cw_max = fls(params->cw_max);
|
||||
|
||||
val = MT76_SET(MT_EDCA_CFG_TXOP, params->txop) |
|
||||
MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) |
|
||||
MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) |
|
||||
MT76_SET(MT_EDCA_CFG_CWMAX, cw_max);
|
||||
val = FIELD_PREP(MT_EDCA_CFG_TXOP, params->txop) |
|
||||
FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
|
||||
FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
|
||||
FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
|
||||
mt76_wr(dev, MT_EDCA_CFG_AC(queue), val);
|
||||
|
||||
val = mt76_rr(dev, MT_WMM_TXOP(queue));
|
||||
|
||||
+2
-2
@@ -98,7 +98,7 @@ mt76x2_mcu_msg_send(struct mt76x2_dev *dev, struct sk_buff *skb, enum mcu_cmd cm
|
||||
|
||||
rxfce = (u32 *) skb->cb;
|
||||
|
||||
if (seq == MT76_GET(MT_RX_FCE_INFO_CMD_SEQ, *rxfce))
|
||||
if (seq == FIELD_GET(MT_RX_FCE_INFO_CMD_SEQ, *rxfce))
|
||||
check_seq = true;
|
||||
|
||||
dev_kfree_skb(skb);
|
||||
@@ -230,7 +230,7 @@ mt76pci_load_firmware(struct mt76x2_dev *dev)
|
||||
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
|
||||
|
||||
val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
|
||||
if (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
|
||||
if (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
|
||||
mt76_set(dev, MT_MCU_COM_REG0, BIT(30));
|
||||
|
||||
/* trigger firmware */
|
||||
|
||||
+26
-26
@@ -24,7 +24,7 @@ mt76x2_adjust_lna_gain(struct mt76x2_dev *dev, int reg, s8 offset)
|
||||
{
|
||||
s8 gain;
|
||||
|
||||
gain = MT76_GET(MT_BBP_AGC_LNA_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
|
||||
gain = FIELD_GET(MT_BBP_AGC_LNA_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
|
||||
gain -= offset / 2;
|
||||
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_GAIN, gain);
|
||||
}
|
||||
@@ -34,7 +34,7 @@ mt76x2_adjust_agc_gain(struct mt76x2_dev *dev, int reg, s8 offset)
|
||||
{
|
||||
s8 gain;
|
||||
|
||||
gain = MT76_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
|
||||
gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
|
||||
gain += offset;
|
||||
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
|
||||
}
|
||||
@@ -408,8 +408,8 @@ static void
|
||||
mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
|
||||
{
|
||||
u32 val = mt76_rr(dev, MT_BBP(AGC, 20));
|
||||
int rssi0 = (s8) MT76_GET(MT_BBP_AGC20_RSSI0, val);
|
||||
int rssi1 = (s8) MT76_GET(MT_BBP_AGC20_RSSI1, val);
|
||||
int rssi0 = (s8) FIELD_GET(MT_BBP_AGC20_RSSI0, val);
|
||||
int rssi1 = (s8) FIELD_GET(MT_BBP_AGC20_RSSI1, val);
|
||||
bool low_gain;
|
||||
u8 *gain = dev->cal.agc_gain_init, gain_delta;
|
||||
|
||||
@@ -449,9 +449,9 @@ mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
|
||||
}
|
||||
|
||||
mt76_wr(dev, MT_BBP(AGC, 8),
|
||||
val | MT76_SET(MT_BBP_AGC_GAIN, gain[0] - gain_delta));
|
||||
val | FIELD_PREP(MT_BBP_AGC_GAIN, gain[0] - gain_delta));
|
||||
mt76_wr(dev, MT_BBP(AGC, 9),
|
||||
val | MT76_SET(MT_BBP_AGC_GAIN, gain[1] - gain_delta));
|
||||
val | FIELD_PREP(MT_BBP_AGC_GAIN, gain[1] - gain_delta));
|
||||
}
|
||||
|
||||
int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
|
||||
@@ -463,26 +463,26 @@ int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
|
||||
u8 channel;
|
||||
|
||||
u32 ext_cca_chan[4] = {
|
||||
[0] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 0) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA1, 1) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
|
||||
[1] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 1) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA1, 0) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
|
||||
[2] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 2) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA1, 3) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
|
||||
[3] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 3) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA1, 2) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) |
|
||||
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
|
||||
[0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
|
||||
[1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
|
||||
[2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
|
||||
[3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
|
||||
FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
|
||||
};
|
||||
int ch_group_index;
|
||||
u8 bw, bw_index;
|
||||
|
||||
+1
-1
@@ -143,7 +143,7 @@ int mt76x2_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
|
||||
if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
|
||||
qsel = 0;
|
||||
|
||||
*tx_info = MT76_SET(MT_TXD_INFO_QSEL, qsel) |
|
||||
*tx_info = FIELD_PREP(MT_TXD_INFO_QSEL, qsel) |
|
||||
MT_TXD_INFO_80211;
|
||||
|
||||
if (!wcid || wcid->hw_key_idx == 0xff)
|
||||
|
||||
@@ -17,65 +17,7 @@
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#ifndef GENMASK
|
||||
#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Power of two check, this will check
|
||||
* if the mask that has been given contains and contiguous set of bits.
|
||||
* Note that we cannot use the is_power_of_2() function since this
|
||||
* check must be done at compile-time.
|
||||
*/
|
||||
#define is_power_of_two(x) ( !((x) & ((x)-1)) )
|
||||
#define low_bit_mask(x) ( ((x)-1) & ~(x) )
|
||||
#define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x))
|
||||
|
||||
/*
|
||||
* Macros to find first set bit in a variable.
|
||||
* These macros behave the same as the __ffs() functions but
|
||||
* the most important difference that this is done during
|
||||
* compile-time rather then run-time.
|
||||
*/
|
||||
#define compile_ffs2(__x) \
|
||||
__builtin_choose_expr(((__x) & 0x1), 0, 1)
|
||||
|
||||
#define compile_ffs4(__x) \
|
||||
__builtin_choose_expr(((__x) & 0x3), \
|
||||
(compile_ffs2((__x))), \
|
||||
(compile_ffs2((__x) >> 2) + 2))
|
||||
|
||||
#define compile_ffs8(__x) \
|
||||
__builtin_choose_expr(((__x) & 0xf), \
|
||||
(compile_ffs4((__x))), \
|
||||
(compile_ffs4((__x) >> 4) + 4))
|
||||
|
||||
#define compile_ffs16(__x) \
|
||||
__builtin_choose_expr(((__x) & 0xff), \
|
||||
(compile_ffs8((__x))), \
|
||||
(compile_ffs8((__x) >> 8) + 8))
|
||||
|
||||
#define compile_ffs32(__x) \
|
||||
__builtin_choose_expr(((__x) & 0xffff), \
|
||||
(compile_ffs16((__x))), \
|
||||
(compile_ffs16((__x) >> 16) + 16))
|
||||
|
||||
|
||||
/*
|
||||
* This macro will check the requirements for the FIELD{8,16,32} macros
|
||||
* The mask should be a constant non-zero contiguous set of bits which
|
||||
* does not exceed the given typelimit.
|
||||
*/
|
||||
#define FIELD_CHECK(__mask) \
|
||||
BUILD_BUG_ON(!(__mask) || !is_valid_mask(__mask))
|
||||
|
||||
#define MT76_SET(_mask, _val) \
|
||||
({ FIELD_CHECK(_mask); (((u32) (_val)) << compile_ffs32(_mask)) & _mask; })
|
||||
|
||||
#define MT76_GET(_mask, _val) \
|
||||
({ FIELD_CHECK(_mask); (u32) (((_val) & _mask) >> compile_ffs32(_mask)); })
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define MT76_INCR(_var, _size) \
|
||||
_var = (((_var) + 1) % _size)
|
||||
|
||||
Reference in New Issue
Block a user