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mt76: dma: do not write cpu_idx on rx queue reset until after refill

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The hardware should only start processing the ring after at least one
buffer has been added

Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2020-02-20 14:57:26 +01:00
parent 53233cdf94
commit a4ae9219e6
1 changed files with 8 additions and 7 deletions
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dma.c
+8 -7
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@@ -132,6 +132,11 @@ mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
writel(q->ndesc, &q->regs->ring_size); writel(q->ndesc, &q->regs->ring_size);
q->head = readl(&q->regs->dma_idx); q->head = readl(&q->regs->dma_idx);
q->tail = q->head; q->tail = q->head;
}
static void
mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
{
writel(q->head, &q->regs->cpu_idx); writel(q->head, &q->regs->cpu_idx);
} }
@@ -185,8 +190,10 @@ mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush)
dev->q_tx[i].swq_queued -= n_swq_queued[i]; dev->q_tx[i].swq_queued -= n_swq_queued[i];
} }
if (flush) if (flush) {
mt76_dma_sync_idx(dev, q); mt76_dma_sync_idx(dev, q);
mt76_dma_kick_queue(dev, q);
}
wake = wake && q->stopped && wake = wake && q->stopped &&
qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8; qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8;
@@ -249,12 +256,6 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
return mt76_dma_get_buf(dev, q, idx, len, info, more); return mt76_dma_get_buf(dev, q, idx, len, info, more);
} }
static void
mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
{
writel(q->head, &q->regs->cpu_idx);
}
static int static int
mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid, mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid,
struct sk_buff *skb, u32 tx_info) struct sk_buff *skb, u32 tx_info)