diff --git a/mt7603_init.c b/mt7603_init.c
index 5027dac0..337eeec5 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -165,6 +165,24 @@ mt7603_dma_sched_init(struct mt7603_dev *dev)
 	mt76_set(dev, MT_SCH_4, BIT(6));
 }
 
+static void
+mt7603_phy_init(struct mt7603_dev *dev)
+{
+	int rx_chains = BIT(dev->rx_chains) - 1;
+	int tx_chains = BIT(dev->tx_chains) - 1;
+
+	mt76_wr(dev, MT_WF_PHY_CR_RXTD(39), 0x0004ba43);
+
+	mt76_rmw(dev, MT_WF_RMAC_RMCR,
+		 (MT_WF_RMAC_RMCR_SMPS_MODE |
+		  MT_WF_RMAC_RMCR_RX_STREAMS),
+		 (MT76_SET(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
+		  MT76_SET(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
+
+	mt76_rmw_field(dev, MT_WF_TMAC_TCR, MT_WF_TMAC_TCR_TX_STREAMS,
+		       tx_chains);
+}
+
 static int
 mt7603_init_hardware(struct mt7603_dev *dev)
 {
@@ -195,6 +213,7 @@ mt7603_init_hardware(struct mt7603_dev *dev)
 		return ret;
 
 	mt7603_dma_sched_init(dev);
+	mt7603_phy_init(dev);
 
 	return 0;
 }
diff --git a/mt7603_regs.h b/mt7603_regs.h
index 7cace5c5..3dd94982 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -109,6 +109,18 @@
 #define MT_PSE_FRP_P2_RQ1		GENMASK(11, 9)
 #define MT_PSE_FRP_P2_RQ2		GENMASK(14, 12)
 
+#define MT_WF_PHY_BASE			0x10000
+#define MT_WF_PHY_OFFSET		0x1000
+#define MT_WF_PHY(ofs)			(MT_WF_PHY_BASE + (ofs))
+
+#define MT_WF_PHY_CR_RXTD_BASE		MT_WF_PHY(0x65c)
+#define MT_WF_PHY_CR_RXTD(n)		(MT_WF_PHY_CR_RXTD_BASE + ((n) * 4))
+
+#define MT_WF_PHY_CR_TSSI_BASE		MT_WF_PHY(0xd00)
+#define MT_WF_PHY_CR_TSSI(phy, n)	(MT_WF_PHY_CR_TSSI_BASE +	\
+					 ((phy) * MT_WF_PHY_OFFSET) +	\
+					 ((n) * 4))
+
 #define MT_WF_AGG_BASE			0x21200
 #define MT_WF_AGG(ofs)			(MT_WF_AGG_BASE + (ofs))
 
@@ -139,6 +151,29 @@
 
 #define MT_WF_ARB_TQCR0			MT_WF_ARB(0x100)
 
+#define MT_WF_TMAC_BASE			0x21600
+#define MT_WF_TMAC(ofs)			(MT_WF_TMAC_BASE + (ofs))
+
+#define MT_WF_TMAC_TCR			MT_WF_TMAC(0x000)
+#define MT_WF_TMAC_TCR_BLINK_SEL	GENMASK(7, 6)
+#define MT_WF_TMAC_TCR_PRE_RTS_GUARD	GENMASK(11, 8)
+#define MT_WF_TMAC_TCR_PRE_RTS_SEC_IDLE	GENMASK(13, 12)
+#define MT_WF_TMAC_TCR_RTS_SIGTA	BIT(14)
+#define MT_WF_TMAC_TCR_LDPC_OFS		BIT(15)
+#define MT_WF_TMAC_TCR_TX_STREAMS	GENMASK(17, 16)
+#define MT_WF_TMAC_SCH_IDLE_SEL		GENMASK(19, 18)
+#define MT_WF_TMAC_SCH_DET_PER_IOD	BIT(20)
+#define MT_WF_TMAC_DCH_DET_DISABLE	BIT(21)
+#define MT_WF_TMAC_TX_RIFS		BIT(22)
+#define MT_WF_TMAC_RX_RIFS_MODE		BIT(23)
+#define MT_WF_TMAC_TXOP_TBTT_CONTROL	BIT(24)
+#define MT_WF_TMAC_TBTT_TX_STOP_CONTROL	BIT(25)
+#define MT_WF_TMAC_TXOP_BURST_STOP	BIT(26)
+#define MT_WF_TMAC_RDG_RA_MODE		BIT(27)
+#define MT_WF_TMAC_RDG_RESP		BIT(29)
+#define MT_WF_TMAC_RDG_GRANT_NO_PENDING	BIT(30)
+#define MT_WF_TMAC_SMOOTHING		BIT(31)
+
 #define MT_WF_RMAC_BASE			0x21800
 #define MT_WF_RMAC(ofs)			(MT_WF_RMAC_BASE + (ofs))
 
@@ -166,6 +201,12 @@
 #define MT_WF_RFCR_DROP_UNWANTED_CTL	BIT(21)
 
 #define MT_WF_RMAC_RMACDR		MT_WF_RMAC(0x078)
+
+#define MT_WF_RMAC_RMCR			MT_WF_RMAC(0x080)
+#define MT_WF_RMAC_RMCR_SMPS_MODE	GENMASK(21, 20)
+#define MT_WF_RMAC_RMCR_RX_STREAMS	GENMASK(24, 22)
+#define MT_WF_RMAC_RMCR_SMPS_RTS	BIT(25)
+
 #define MT_WF_RMAC_MAXMINLEN		MT_WF_RMAC(0x098)
 #define MT_WF_RFCR1			MT_WF_RMAC(0x0a4)
 #define MT_WF_RMAC_TMR_PA		MT_WF_RMAC(0x0e0)