diff --git a/mt7603_init.c b/mt7603_init.c
index 14ad4f4f..2c20295a 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -231,6 +231,10 @@ mt7603_mac_init(struct mt7603_dev *dev)
 	/* Enable RX group to MCU */
 	mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
 
+	mt76_rmw_field(dev, MT_AGG_PCR, MT_AGG_PCR_RTS_PKT_THR, 3);
+	mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN);
+	mt76_wr(dev, MT_RXREQ, 4);
+
 	/* Configure all rx packets to HIF */
 	mt76_wr(dev, MT_DMA_RCFR0, 0xc0200000);
 
diff --git a/mt7603_regs.h b/mt7603_regs.h
index 114735b8..ce076855 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -149,6 +149,10 @@
 #define MT_AGG_BA_SIZE_LIMIT_1		MT_WF_AGG(0x04c)
 #define MT_AGG_BA_SIZE_LIMIT_SHIFT	8
 
+#define MT_AGG_PCR			MT_WF_AGG(0x054)
+#define MT_AGG_PCR_RTS_THR		GENMASK(19, 0)
+#define MT_AGG_PCR_RTS_PKT_THR		GENMASK(31, 25)
+
 #define MT_AGG_CONTROL			MT_WF_AGG(0x070)
 #define MT_AGG_CONTROL_NO_BA_RULE	BIT(0)
 #define MT_AGG_CONTROL_NO_BA_AR_RULE	BIT(1)
@@ -241,12 +245,24 @@
 #define MT_TIMEOUT_VAL_PLCP		GENMASK(15, 0)
 #define MT_TIMEOUT_VAL_CCA		GENMASK(31, 16)
 
+#define MT_RXREQ			MT_WF_TMAC(0x0a0)
+#define MT_RXREQ_DELAY			GENMASK(8, 0)
+
 #define MT_IFS				MT_WF_TMAC(0x0a4)
 #define MT_IFS_EIFS			GENMASK(8, 0)
 #define MT_IFS_RIFS			GENMASK(14, 10)
 #define MT_IFS_SIFS			GENMASK(22, 16)
 #define MT_IFS_SLOT			GENMASK(30, 24)
 
+#define MT_TMAC_PCR			MT_WF_TMAC(0x0b4)
+#define MT_TMAC_PCR_RATE		GENMASK(8, 0)
+#define MT_TMAC_PCR_RATE_FIXED		BIT(15)
+#define MT_TMAC_PCR_ANT_ID		GENMASK(21, 16)
+#define MT_TMAC_PCR_ANT_ID_SEL		BIT(22)
+#define MT_TMAC_PCR_SPE_EN		BIT(23)
+#define MT_TMAC_PCR_ANT_PRI		GENMASK(26, 24)
+#define MT_TMAC_PCR_ANT_PRI_SEL		GENMASK(27)
+
 #define MT_WF_RMAC_BASE			0x21800
 #define MT_WF_RMAC(ofs)			(MT_WF_RMAC_BASE + (ofs))