mirror of
https://github.com/outbackdingo/mt76.git
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mt76: sdio: move common code in mt76_sdio module
Move sdio common code in mt76_sdio module. This is a preliminary patch to support mt7921s devices. Co-developed-by: Sean Wang <[email protected]> Signed-off-by: Sean Wang <[email protected]> Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Lorenzo Bianconi
committed by
Felix Fietkau
Felix Fietkau
parent
f0dedcf6aa
commit
5079d5b0b1
@@ -16,6 +16,271 @@
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#include <linux/kthread.h>
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#include "mt76.h"
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#include "sdio.h"
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static u32 mt76s_read_whisr(struct mt76_dev *dev)
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{
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return sdio_readl(dev->sdio.func, MCR_WHISR, NULL);
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}
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u32 mt76s_read_pcr(struct mt76_dev *dev)
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{
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struct mt76_sdio *sdio = &dev->sdio;
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return sdio_readl(sdio->func, MCR_WHLPCR, NULL);
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}
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EXPORT_SYMBOL_GPL(mt76s_read_pcr);
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static u32 mt76s_read_mailbox(struct mt76_dev *dev, u32 offset)
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{
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struct sdio_func *func = dev->sdio.func;
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u32 val = ~0, status;
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int err;
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sdio_claim_host(func);
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sdio_writel(func, offset, MCR_H2DSM0R, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting address [err=%d]\n", err);
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goto out;
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}
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sdio_writel(func, H2D_SW_INT_READ, MCR_WSICR, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting read mode [err=%d]\n", err);
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goto out;
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}
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err = readx_poll_timeout(mt76s_read_whisr, dev, status,
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status & H2D_SW_INT_READ, 0, 1000000);
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if (err < 0) {
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dev_err(dev->dev, "query whisr timeout\n");
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goto out;
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}
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sdio_writel(func, H2D_SW_INT_READ, MCR_WHISR, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting read mode [err=%d]\n", err);
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goto out;
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}
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val = sdio_readl(func, MCR_H2DSM0R, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed reading h2dsm0r [err=%d]\n", err);
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goto out;
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}
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if (val != offset) {
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dev_err(dev->dev, "register mismatch\n");
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val = ~0;
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goto out;
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}
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val = sdio_readl(func, MCR_D2HRM1R, &err);
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if (err < 0)
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dev_err(dev->dev, "failed reading d2hrm1r [err=%d]\n", err);
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out:
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sdio_release_host(func);
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return val;
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}
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static void mt76s_write_mailbox(struct mt76_dev *dev, u32 offset, u32 val)
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{
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struct sdio_func *func = dev->sdio.func;
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u32 status;
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int err;
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sdio_claim_host(func);
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sdio_writel(func, offset, MCR_H2DSM0R, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting address [err=%d]\n", err);
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goto out;
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}
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sdio_writel(func, val, MCR_H2DSM1R, &err);
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if (err < 0) {
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dev_err(dev->dev,
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"failed setting write value [err=%d]\n", err);
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goto out;
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}
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sdio_writel(func, H2D_SW_INT_WRITE, MCR_WSICR, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting write mode [err=%d]\n", err);
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goto out;
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}
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err = readx_poll_timeout(mt76s_read_whisr, dev, status,
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status & H2D_SW_INT_WRITE, 0, 1000000);
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if (err < 0) {
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dev_err(dev->dev, "query whisr timeout\n");
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goto out;
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}
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sdio_writel(func, H2D_SW_INT_WRITE, MCR_WHISR, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed setting write mode [err=%d]\n", err);
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goto out;
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}
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val = sdio_readl(func, MCR_H2DSM0R, &err);
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if (err < 0) {
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dev_err(dev->dev, "failed reading h2dsm0r [err=%d]\n", err);
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goto out;
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}
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if (val != offset)
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dev_err(dev->dev, "register mismatch\n");
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out:
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sdio_release_host(func);
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}
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u32 mt76s_rr(struct mt76_dev *dev, u32 offset)
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{
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if (test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state))
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return dev->mcu_ops->mcu_rr(dev, offset);
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else
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return mt76s_read_mailbox(dev, offset);
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}
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EXPORT_SYMBOL_GPL(mt76s_rr);
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void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val)
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{
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if (test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state))
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dev->mcu_ops->mcu_wr(dev, offset, val);
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else
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mt76s_write_mailbox(dev, offset, val);
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}
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EXPORT_SYMBOL_GPL(mt76s_wr);
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u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
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{
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val |= mt76s_rr(dev, offset) & ~mask;
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mt76s_wr(dev, offset, val);
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return val;
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}
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EXPORT_SYMBOL_GPL(mt76s_rmw);
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void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
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const void *data, int len)
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{
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const u32 *val = data;
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int i;
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for (i = 0; i < len / sizeof(u32); i++) {
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mt76s_wr(dev, offset, val[i]);
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offset += sizeof(u32);
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}
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}
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EXPORT_SYMBOL_GPL(mt76s_write_copy);
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void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
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void *data, int len)
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{
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u32 *val = data;
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int i;
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for (i = 0; i < len / sizeof(u32); i++) {
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val[i] = mt76s_rr(dev, offset);
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offset += sizeof(u32);
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}
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}
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EXPORT_SYMBOL_GPL(mt76s_read_copy);
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int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
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const struct mt76_reg_pair *data,
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int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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mt76s_wr(dev, data->reg, data->value);
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data++;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76s_wr_rp);
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int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
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struct mt76_reg_pair *data, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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data->value = mt76s_rr(dev, data->reg);
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data++;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt76s_rd_rp);
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int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func)
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{
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u32 status, ctrl;
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int ret;
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sdio_claim_host(func);
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ret = sdio_enable_func(func);
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if (ret < 0)
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goto release;
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/* Get ownership from the device */
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sdio_writel(func, WHLPCR_INT_EN_CLR | WHLPCR_FW_OWN_REQ_CLR,
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MCR_WHLPCR, &ret);
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if (ret < 0)
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goto disable_func;
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ret = readx_poll_timeout(mt76s_read_pcr, dev, status,
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status & WHLPCR_IS_DRIVER_OWN, 2000, 1000000);
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if (ret < 0) {
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dev_err(dev->dev, "Cannot get ownership from device");
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goto disable_func;
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}
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ret = sdio_set_block_size(func, 512);
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if (ret < 0)
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goto disable_func;
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/* Enable interrupt */
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sdio_writel(func, WHLPCR_INT_EN_SET, MCR_WHLPCR, &ret);
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if (ret < 0)
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goto disable_func;
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ctrl = WHIER_RX0_DONE_INT_EN | WHIER_TX_DONE_INT_EN;
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sdio_writel(func, ctrl, MCR_WHIER, &ret);
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if (ret < 0)
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goto disable_func;
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/* set WHISR as read clear and Rx aggregation number as 16 */
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ctrl = FIELD_PREP(MAX_HIF_RX_LEN_NUM, 16);
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sdio_writel(func, ctrl, MCR_WHCR, &ret);
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if (ret < 0)
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goto disable_func;
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ret = sdio_claim_irq(func, mt76s_sdio_irq);
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if (ret < 0)
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goto disable_func;
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sdio_release_host(func);
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return 0;
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disable_func:
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sdio_disable_func(func);
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release:
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sdio_release_host(func);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mt76s_hw_init);
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int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid)
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{
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