From 3ffc429b5b72ecc1187f4c43f64062acadf04ea0 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 26 Feb 2016 21:07:59 +0100 Subject: [PATCH] mt7603: issue rate table updates via registers Signed-off-by: Felix Fietkau --- mt7603_mac.c | 43 +++++++++++++++++++++++++++++++++---------- mt7603_regs.h | 21 +++++++++++++++++++++ 2 files changed, 54 insertions(+), 10 deletions(-) diff --git a/mt7603_mac.c b/mt7603_mac.c index 4be94118..0ad478d9 100644 --- a/mt7603_mac.c +++ b/mt7603_mac.c @@ -449,37 +449,60 @@ void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta) bool stbc = false; int n_rates = sta->n_rates; u8 bw, bw_prev, bw_idx = 0; - u16 val; + u16 val[4]; int i; for (i = n_rates; i < 4; i++) rates[i] = rates[n_rates - 1]; - val = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); + val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); mt76_rmw_field(dev, addr + 9 * 4, MT_WTBL2_W9_BW_CAP, bw); - mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE1, val); + mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE1, val[0]); bw_prev = bw; - val = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); - mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE2, val); + val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); + mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE2, val[1]); if (bw_prev < bw && !bw_idx) bw_idx = 1; bw_prev = bw; - val = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); - mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE3_LO, val); - mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE3_HI, val >> 4); + val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); + mt76_rmw_field(dev, addr + 10 * 4, MT_WTBL2_W10_RATE3_LO, val[2]); + mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE3_HI, val[2] >> 4); if (bw_prev < bw && !bw_idx) bw_idx = 2; bw_prev = bw; - val = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); - mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE4, val); + val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); + mt76_rmw_field(dev, addr + 11 * 4, MT_WTBL2_W11_RATE4, val[3]); if (bw_prev < bw && !bw_idx) bw_idx = 3; mt76_rmw_field(dev, addr + 9 * 4, MT_WTBL2_W9_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7); + + mt76_wr(dev, MT_WTBL_RIUCR0, mt76_rr(dev, addr + 9 * 4)); + + mt76_wr(dev, MT_WTBL_RIUCR1, + MT76_SET(MT_WTBL_RIUCR1_RATE0, val[0]) | + MT76_SET(MT_WTBL_RIUCR1_RATE1, val[1]) | + MT76_SET(MT_WTBL_RIUCR1_RATE2_LO, val[2])); + + mt76_wr(dev, MT_WTBL_RIUCR2, + MT76_SET(MT_WTBL_RIUCR2_RATE2_HI, val[2] >> 8) | + MT76_SET(MT_WTBL_RIUCR2_RATE3, val[3]) | + MT76_SET(MT_WTBL_RIUCR2_RATE4, val[0]) | + MT76_SET(MT_WTBL_RIUCR2_RATE5_LO, val[1])); + + mt76_wr(dev, MT_WTBL_RIUCR3, + MT76_SET(MT_WTBL_RIUCR3_RATE5_HI, val[1] >> 4) | + MT76_SET(MT_WTBL_RIUCR3_RATE6, val[2]) | + MT76_SET(MT_WTBL_RIUCR3_RATE7, val[3])); + + mt76_wr(dev, MT_WTBL_UPDATE, + MT76_SET(MT_WTBL_UPDATE_WLAN_IDX, wcid) | + MT_WTBL_UPDATE_RATE_UPDATE | + MT_WTBL_UPDATE_TX_COUNT_CLEAR); } static enum mt7603_cipher_type diff --git a/mt7603_regs.h b/mt7603_regs.h index 2daa53a0..5561abb1 100644 --- a/mt7603_regs.h +++ b/mt7603_regs.h @@ -420,6 +420,27 @@ enum { #define MT_WTBL1_BASE 0x28000 +#define MT_WTBL_ON_BASE (MT_WTBL1_BASE + 0x2000) +#define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n)) + +#define MT_WTBL_RIUCR0 MT_WTBL_ON(0x200) + +#define MT_WTBL_RIUCR1 MT_WTBL_ON(0x204) +#define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0) +#define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12) +#define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24) + +#define MT_WTBL_RIUCR2 MT_WTBL_ON(0x208) +#define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0) +#define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4) +#define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16) +#define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28) + +#define MT_WTBL_RIUCR3 MT_WTBL_ON(0x20c) +#define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0) +#define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8) +#define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20) + #define MT_PCIE_REMAP_BASE_1 0x40000 #define MT_PCIE_REMAP_BASE_2 0x80000