From 3a18d180c677b73792bee3eaddd2c60ca101f2ae Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 26 Feb 2016 19:30:30 +0100 Subject: [PATCH] mt7603: clean up ARB SCR register definition Signed-off-by: Felix Fietkau --- mt7603_beacon.c | 4 ++-- mt7603_init.c | 2 +- mt7603_mac.c | 4 ++-- mt7603_regs.h | 18 +++++++++--------- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/mt7603_beacon.c b/mt7603_beacon.c index f61b02b0..cb626fe9 100644 --- a/mt7603_beacon.c +++ b/mt7603_beacon.c @@ -125,7 +125,7 @@ void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval) if (!dev->beacon_mask) { mt7603_irq_disable(dev, MT_INT_MAC_IRQ3); - mt76_clear(dev, MT_WF_ARB_SCR, MT_WF_ARB_BCNQ_OPMODE_MASK); + mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK); mt76_wr(dev, MT_HW_INT_MASK(3), 0); return; } @@ -135,7 +135,7 @@ void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval) mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */ - mt76_rmw_field(dev, MT_WF_ARB_SCR, MT_WF_ARB_BCNQ_OPMODE_MASK, + mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK, MT_BCNQ_OPMODE_AP); mt76_wr(dev, MT_PRE_TBTT, pre_tbtt); diff --git a/mt7603_init.c b/mt7603_init.c index 8f68539b..b0ccc4a9 100644 --- a/mt7603_init.c +++ b/mt7603_init.c @@ -70,7 +70,7 @@ mt7603_mac_early_init(struct mt7603_dev *dev) { mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850); - mt76_clear(dev, MT_WF_ARB_SCR, MT_WF_ARB_TX_DISABLE | MT_WF_ARB_RX_DISABLE); + mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); diff --git a/mt7603_mac.c b/mt7603_mac.c index dcc099ed..4be94118 100644 --- a/mt7603_mac.c +++ b/mt7603_mac.c @@ -873,14 +873,14 @@ void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, void mt7603_mac_start(struct mt7603_dev *dev) { - mt76_clear(dev, MT_WF_ARB_SCR, MT_WF_ARB_TX_DISABLE | MT_WF_ARB_RX_DISABLE); + mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); } void mt7603_mac_stop(struct mt7603_dev *dev) { - mt76_set(dev, MT_WF_ARB_SCR, MT_WF_ARB_TX_DISABLE | MT_WF_ARB_RX_DISABLE); + mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); } diff --git a/mt7603_regs.h b/mt7603_regs.h index 2076b507..3880ed29 100644 --- a/mt7603_regs.h +++ b/mt7603_regs.h @@ -208,15 +208,15 @@ #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7) #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8) -#define MT_WF_ARB_SCR MT_WF_ARB(0x080) -#define MT_WF_ARB_BCNQ_OPMODE_MASK GENMASK(1, 0) -#define MT_WF_ARB_BCNQ_OPMODE_SHIFT(n) (n * 2) -#define MT_WF_ARB_TX_DISABLE BIT(8) -#define MT_WF_ARB_RX_DISABLE BIT(9) -#define MT_WF_ARB_BCNQ_EMPTY_SKIP BIT(28) -#define MT_WF_ARB_TTTT_BTIM_PRIO BIT(29) -#define MT_WF_ARB_TBTT_BCN_PRIO BIT(30) -#define MT_WF_ARB_TBTT_BCAST_PRIO BIT(31) +#define MT_ARB_SCR MT_WF_ARB(0x080) +#define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0) +#define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n) (n * 2) +#define MT_ARB_SCR_TX_DISABLE BIT(8) +#define MT_ARB_SCR_RX_DISABLE BIT(9) +#define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28) +#define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29) +#define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30) +#define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31) enum { MT_BCNQ_OPMODE_STA = 0,