diff --git a/mt7603_init.c b/mt7603_init.c
index 08fbb711..a03a3d9a 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -215,6 +215,11 @@ mt7603_mac_init(struct mt7603_dev *dev)
 	mt76_wr(dev, MT_MAC_ADDR0(0), get_unaligned_le32(dev_addr));
 	mt76_wr(dev, MT_MAC_ADDR1(0),
 		get_unaligned_le16(dev_addr + 4) | MT_MAC_ADDR1_VALID);
+
+	mt76_wr(dev, MT_AGG_ARUCR, 0);
+	mt76_wr(dev, MT_AGG_ARDCR, ~0);
+	mt76_wr(dev, MT_AGG_ARCR, (MT_AGG_ARCR_INIT_RATE1 |
+				   MT76_SET(MT_AGG_ARCR_RTS_RATE_THR, 2)));
 }
 
 static int
diff --git a/mt7603_regs.h b/mt7603_regs.h
index 0fd7b5a7..d0120da8 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -124,6 +124,23 @@
 #define MT_WF_AGG_BASE			0x21200
 #define MT_WF_AGG(ofs)			(MT_WF_AGG_BASE + (ofs))
 
+#define MT_AGG_ARCR			MT_WF_AGG(0x010)
+#define MT_AGG_ARCR_INIT_RATE1		BIT(0)
+#define MT_AGG_ARCR_FB_SGI_DISABLE	BIT(1)
+#define MT_AGG_ARCR_RATE8_DOWN_WRAP	BIT(2)
+#define MT_AGG_ARCR_RTS_RATE_THR	GENMASK(12, 8)
+#define MT_AGG_ARCR_RATE_DOWN_RATIO	GENMASK(17, 16)
+#define MT_AGG_ARCR_RATE_DOWN_RATIO_EN	BIT(19)
+#define MT_AGG_ARCR_RATE_UP_EXTRA_TH	GENMASK(22, 20)
+#define MT_AGG_ARCR_SPE_DIS_TH		GENMASK(27, 24)
+
+
+#define MT_AGG_ARUCR			MT_WF_AGG(0x014)
+#define MT_AGG_ARDCR			MT_WF_AGG(0x018)
+#define MT_AGG_ARxCR_LIMIT_SHIFT(_n)	(3 * _n)
+#define MT_AGG_ARxCR_LIMIT(_n)		GENMASK(3 + MT_AGG_ARxCR_LIMIT_SHIFT(_n), \
+						MT_AGG_ARxCR_LIMIT_SHIFT(_n))
+
 #define MT_AGG_TMP			MT_WF_AGG(0x0d8)
 
 #define MT_AGG_BWCR			MT_WF_AGG(0x0ec)