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replace mt76 prefix with mt76x2 in preparation for splitting the driver for more chipset support

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Signed-off-by: Felix Fietkau <[email protected]>
This commit is contained in:
Felix Fietkau
2015-12-06 16:54:53 +01:00
parent 2e4443a51f
commit 31c11fdb05
21 changed files with 1154 additions and 1154 deletions
Download Patch File Download Diff File Expand all files Collapse all files
core.c
+22 -22
View File
@@ -15,14 +15,14 @@
#include "mt76.h"
#include "trace.h"
bool mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
bool mt76x2_poll(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
int timeout)
{
u32 cur;
timeout /= 10;
do {
cur = mt76_rr(dev, offset) & mask;
cur = mt76x2_rr(dev, offset) & mask;
if (cur == val)
return true;
@@ -32,14 +32,14 @@ bool mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
return false;
}
bool mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
int timeout)
{
u32 cur;
timeout /= 10;
do {
cur = mt76_rr(dev, offset) & mask;
cur = mt76x2_rr(dev, offset) & mask;
if (cur == val)
return true;
@@ -49,34 +49,34 @@ bool mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
return false;
}
void mt76_write_reg_pairs(struct mt76_dev *dev,
const struct mt76_reg_pair *data, int len)
void mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
const struct mt76x2_reg_pair *data, int len)
{
while (len > 0) {
mt76_wr(dev, data->reg, data->value);
mt76x2_wr(dev, data->reg, data->value);
len--;
data++;
}
}
void mt76_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set)
void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set)
{
unsigned long flags;
spin_lock_irqsave(&dev->irq_lock, flags);
dev->irqmask &= ~clear;
dev->irqmask |= set;
mt76_wr(dev, MT_INT_MASK_CSR, dev->irqmask);
mt76x2_wr(dev, MT_INT_MASK_CSR, dev->irqmask);
spin_unlock_irqrestore(&dev->irq_lock, flags);
}
irqreturn_t mt76_irq_handler(int irq, void *dev_instance)
irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance)
{
struct mt76_dev *dev = dev_instance;
struct mt76x2_dev *dev = dev_instance;
u32 intr;
intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
intr = mt76x2_rr(dev, MT_INT_SOURCE_CSR);
mt76x2_wr(dev, MT_INT_SOURCE_CSR, intr);
if (!test_bit(MT76_STATE_INITIALIZED, &dev->state))
return IRQ_NONE;
@@ -86,17 +86,17 @@ irqreturn_t mt76_irq_handler(int irq, void *dev_instance)
intr &= dev->irqmask;
if (intr & MT_INT_TX_DONE_ALL) {
mt76_irq_disable(dev, MT_INT_TX_DONE_ALL);
mt76x2_irq_disable(dev, MT_INT_TX_DONE_ALL);
tasklet_schedule(&dev->tx_tasklet);
}
if (intr & MT_INT_RX_DONE(0)) {
mt76_irq_disable(dev, MT_INT_RX_DONE(0));
mt76x2_irq_disable(dev, MT_INT_RX_DONE(0));
napi_schedule(&dev->napi);
}
if (intr & MT_INT_RX_DONE(1)) {
mt76_irq_disable(dev, MT_INT_RX_DONE(1));
mt76x2_irq_disable(dev, MT_INT_RX_DONE(1));
tasklet_schedule(&dev->rx_tasklet);
}
@@ -105,26 +105,26 @@ irqreturn_t mt76_irq_handler(int irq, void *dev_instance)
/* send buffered multicast frames now */
if (intr & MT_INT_TBTT)
mt76_kick_queue(dev, &dev->q_tx[MT_TXQ_PSD]);
mt76x2_kick_queue(dev, &dev->q_tx[MT_TXQ_PSD]);
if (intr & MT_INT_TX_STAT) {
mt76_mac_poll_tx_status(dev, true);
mt76x2_mac_poll_tx_status(dev, true);
tasklet_schedule(&dev->tx_tasklet);
}
return IRQ_HANDLED;
}
int mt76_set_channel(struct mt76_dev *dev, struct cfg80211_chan_def *chandef)
int mt76x2_set_channel(struct mt76x2_dev *dev, struct cfg80211_chan_def *chandef)
{
int ret;
tasklet_disable(&dev->pre_tbtt_tasklet);
cancel_delayed_work_sync(&dev->cal_work);
mt76_mac_stop(dev, true);
ret = mt76_phy_set_channel(dev, chandef);
mt76_mac_resume(dev);
mt76x2_mac_stop(dev, true);
ret = mt76x2_phy_set_channel(dev, chandef);
mt76x2_mac_resume(dev);
tasklet_enable(&dev->pre_tbtt_tasklet);
return ret;
debugfs.c
+14 -14
View File
@@ -15,30 +15,30 @@
#include "mt76.h"
static int
mt76_reg_set(void *data, u64 val)
mt76x2_reg_set(void *data, u64 val)
{
struct mt76_dev *dev = data;
struct mt76x2_dev *dev = data;
mt76_wr(dev, dev->debugfs_reg, val);
mt76x2_wr(dev, dev->debugfs_reg, val);
return 0;
}
static int
mt76_reg_get(void *data, u64 *val)
mt76x2_reg_get(void *data, u64 *val)
{
struct mt76_dev *dev = data;
struct mt76x2_dev *dev = data;
*val = mt76_rr(dev, dev->debugfs_reg);
*val = mt76x2_rr(dev, dev->debugfs_reg);
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_regval, mt76_reg_get, mt76_reg_set, "0x%08llx\n");
DEFINE_SIMPLE_ATTRIBUTE(fops_regval, mt76x2_reg_get, mt76x2_reg_set, "0x%08llx\n");
static int
mt76_ampdu_stat_read(struct seq_file *file, void *data)
mt76x2_ampdu_stat_read(struct seq_file *file, void *data)
{
struct mt76_dev *dev = file->private;
struct mt76x2_dev *dev = file->private;
int i, j;
for (i = 0; i < 4; i++) {
@@ -60,9 +60,9 @@ mt76_ampdu_stat_read(struct seq_file *file, void *data)
}
static int
mt76_ampdu_stat_open(struct inode *inode, struct file *f)
mt76x2_ampdu_stat_open(struct inode *inode, struct file *f)
{
return single_open(f, mt76_ampdu_stat_read, inode->i_private);
return single_open(f, mt76x2_ampdu_stat_read, inode->i_private);
}
static void
@@ -78,7 +78,7 @@ seq_puts_array(struct seq_file *file, const char *str, s8 *val, int len)
static int read_txpower(struct seq_file *file, void *data)
{
struct mt76_dev *dev = dev_get_drvdata(file->private);
struct mt76x2_dev *dev = dev_get_drvdata(file->private);
seq_printf(file, "Target power: %d\n", dev->target_power);
@@ -96,13 +96,13 @@ static int read_txpower(struct seq_file *file, void *data)
}
static const struct file_operations fops_ampdu_stat = {
.open = mt76_ampdu_stat_open,
.open = mt76x2_ampdu_stat_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
void mt76_init_debugfs(struct mt76_dev *dev)
void mt76x2_init_debugfs(struct mt76x2_dev *dev)
{
struct dentry *dir;
dma.c
+109 -109
View File
@@ -14,24 +14,24 @@
#include "mt76.h"
#include "dma.h"
struct mt76_txwi_cache {
struct mt76_txwi txwi;
struct mt76x2_txwi_cache {
struct mt76x2_txwi txwi;
dma_addr_t dma_addr;
struct list_head list;
};
static inline int
mt76_rx_buf_offset(struct mt76_dev *dev)
mt76x2_rx_buf_offset(struct mt76x2_dev *dev)
{
BUILD_BUG_ON(MT_RX_HEADROOM < sizeof(struct mt76_rxwi));
BUILD_BUG_ON(MT_RX_HEADROOM < sizeof(struct mt76x2_rxwi));
return MT_RX_HEADROOM - sizeof(struct mt76_rxwi);
return MT_RX_HEADROOM - sizeof(struct mt76x2_rxwi);
}
static struct mt76_txwi_cache *
mt76_alloc_txwi(struct mt76_dev *dev)
static struct mt76x2_txwi_cache *
mt76x2_alloc_txwi(struct mt76x2_dev *dev)
{
struct mt76_txwi_cache *t;
struct mt76x2_txwi_cache *t;
dma_addr_t addr;
int size;
@@ -46,14 +46,14 @@ mt76_alloc_txwi(struct mt76_dev *dev)
return t;
}
static struct mt76_txwi_cache *
__mt76_get_txwi(struct mt76_dev *dev)
static struct mt76x2_txwi_cache *
__mt76x2_get_txwi(struct mt76x2_dev *dev)
{
struct mt76_txwi_cache *t = NULL;
struct mt76x2_txwi_cache *t = NULL;
spin_lock_bh(&dev->lock);
if (!list_empty(&dev->txwi_cache)) {
t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
t = list_first_entry(&dev->txwi_cache, struct mt76x2_txwi_cache,
list);
list_del(&t->list);
}
@@ -62,19 +62,19 @@ __mt76_get_txwi(struct mt76_dev *dev)
return t;
}
static struct mt76_txwi_cache *
mt76_get_txwi(struct mt76_dev *dev)
static struct mt76x2_txwi_cache *
mt76x2_get_txwi(struct mt76x2_dev *dev)
{
struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
struct mt76x2_txwi_cache *t = __mt76x2_get_txwi(dev);
if (t)
return t;
return mt76_alloc_txwi(dev);
return mt76x2_alloc_txwi(dev);
}
static void
mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
mt76x2_put_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi_cache *t)
{
if (!t)
return;
@@ -85,12 +85,12 @@ mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
}
static int
mt76_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q)
mt76x2_alloc_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q)
{
int size;
int i;
size = q->ndesc * sizeof(struct mt76_desc);
size = q->ndesc * sizeof(struct mt76x2_desc);
q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL);
if (!q->desc)
return -ENOMEM;
@@ -112,16 +112,16 @@ mt76_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q)
return 0;
}
void mt76_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
void mt76x2_kick_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q)
{
iowrite32(q->head, &q->regs->cpu_idx);
}
static int
mt76_queue_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
mt76x2_queue_add_buf(struct mt76x2_dev *dev, struct mt76x2_queue *q,
u32 buf0, int len0, u32 buf1, int len1, u32 info)
{
struct mt76_desc *desc;
struct mt76x2_desc *desc;
u32 ctrl;
int idx;
@@ -145,16 +145,16 @@ mt76_queue_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
}
static int
mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q,
mt76x2_dma_add_rx_buf(struct mt76x2_dev *dev, struct mt76x2_queue *q,
dma_addr_t addr, int len)
{
int offset = mt76_rx_buf_offset(dev);
int offset = mt76x2_rx_buf_offset(dev);
return mt76_queue_add_buf(dev, q, addr + offset, len - offset, 0, 0, 0);
return mt76x2_queue_add_buf(dev, q, addr + offset, len - offset, 0, 0, 0);
}
static int
mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
mt76x2_dma_rx_fill(struct mt76x2_dev *dev, struct mt76x2_queue *q)
{
dma_addr_t addr;
void *buf;
@@ -181,7 +181,7 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
}
if (frames)
mt76_kick_queue(dev, q);
mt76x2_kick_queue(dev, q);
spin_unlock_bh(&q->lock);
@@ -189,10 +189,10 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
}
static int
mt76_dma_tx_queue_mcu(struct mt76_dev *dev, enum mt76_txq_id qid,
mt76x2_dma_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76x2_txq_id qid,
struct sk_buff *skb, int cmd, int seq)
{
struct mt76_queue *q = &dev->q_tx[qid];
struct mt76x2_queue *q = &dev->q_tx[qid];
dma_addr_t addr;
u32 tx_info;
int idx;
@@ -208,38 +208,38 @@ mt76_dma_tx_queue_mcu(struct mt76_dev *dev, enum mt76_txq_id qid,
return -ENOMEM;
spin_lock_bh(&q->lock);
idx = mt76_queue_add_buf(dev, q, addr, skb->len, 0, 0, tx_info);
idx = mt76x2_queue_add_buf(dev, q, addr, skb->len, 0, 0, tx_info);
q->entry[idx].skb = skb;
mt76_kick_queue(dev, q);
mt76x2_kick_queue(dev, q);
spin_unlock_bh(&q->lock);
return 0;
}
static int
mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
struct sk_buff *skb, struct mt76_wcid *wcid,
mt76x2_dma_tx_queue_skb(struct mt76x2_dev *dev, struct mt76x2_queue *q,
struct sk_buff *skb, struct mt76x2_wcid *wcid,
struct ieee80211_sta *sta)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct mt76_txwi_cache *t;
struct mt76x2_txwi_cache *t;
dma_addr_t addr;
u32 tx_info = 0;
int idx, ret, len;
int qsel = MT_QSEL_EDCA;
ret = -ENOMEM;
t = mt76_get_txwi(dev);
t = mt76x2_get_txwi(dev);
if (!t)
goto free;
dma_sync_single_for_cpu(dev->dev, t->dma_addr, sizeof(t->txwi),
DMA_TO_DEVICE);
mt76_mac_write_txwi(dev, &t->txwi, skb, wcid, sta);
mt76x2_mac_write_txwi(dev, &t->txwi, skb, wcid, sta);
dma_sync_single_for_device(dev->dev, t->dma_addr, sizeof(t->txwi),
DMA_TO_DEVICE);
ret = mt76_insert_hdr_pad(skb);
ret = mt76x2_insert_hdr_pad(skb);
if (ret)
goto put_txwi;
@@ -247,7 +247,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
qsel = 0;
len = skb->len + sizeof(t->txwi);
len += mt76_mac_skb_tx_overhead(dev, skb);
len += mt76x2_mac_skb_tx_overhead(dev, skb);
tx_info = MT76_SET(MT_TXD_INFO_LEN, len) |
MT76_SET(MT_TXD_INFO_QSEL, qsel) |
MT_TXD_INFO_80211;
@@ -259,7 +259,7 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
if (dma_mapping_error(dev->dev, addr))
goto put_txwi;
idx = mt76_queue_add_buf(dev, q, t->dma_addr, sizeof(t->txwi),
idx = mt76x2_queue_add_buf(dev, q, t->dma_addr, sizeof(t->txwi),
addr, skb->len, tx_info);
q->entry[idx].skb = skb;
q->entry[idx].txwi = t;
@@ -267,14 +267,14 @@ mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
return idx;
put_txwi:
mt76_put_txwi(dev, t);
mt76x2_put_txwi(dev, t);
free:
ieee80211_free_txskb(dev->hw, skb);
return ret;
}
static int
mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
mt76x2_dma_dequeue(struct mt76x2_dev *dev, struct mt76x2_queue *q, bool flush)
{
int ret = -1;
@@ -292,12 +292,12 @@ mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
}
static void
mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
mt76x2_dma_tx_cleanup_idx(struct mt76x2_dev *dev, struct mt76x2_queue *q, int idx,
bool flush, bool *schedule)
{
struct mt76_queue_entry *e = &q->entry[idx];
struct mt76x2_queue_entry *e = &q->entry[idx];
struct sk_buff *skb = e->skb;
struct mt76_txwi_cache *txwi = e->txwi;
struct mt76x2_txwi_cache *txwi = e->txwi;
dma_addr_t skb_addr;
*schedule = e->schedule;
@@ -317,12 +317,12 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
return;
}
mt76_mac_queue_txdone(dev, skb, &txwi->txwi);
mt76_put_txwi(dev, txwi);
mt76x2_mac_queue_txdone(dev, skb, &txwi->txwi);
mt76x2_put_txwi(dev, txwi);
}
static void
mt76_tx_cleanup_entry(struct mt76_dev *dev, struct mt76_queue *q, int idx,
mt76x2_tx_cleanup_entry(struct mt76x2_dev *dev, struct mt76x2_queue *q, int idx,
bool flush)
{
bool schedule;
@@ -331,12 +331,12 @@ mt76_tx_cleanup_entry(struct mt76_dev *dev, struct mt76_queue *q, int idx,
if (schedule) {
q->swq_queued--;
if (!flush)
mt76_txq_schedule(dev, q);
mt76x2_txq_schedule(dev, q);
}
}
static void
mt76_tx_cleanup_queue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
mt76x2_tx_cleanup_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q, bool flush)
{
int last;
@@ -348,7 +348,7 @@ mt76_tx_cleanup_queue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
last = ioread32(&q->regs->dma_idx);
while (q->queued && q->tail != last) {
mt76_tx_cleanup_entry(dev, q, q->tail, flush);
mt76x2_tx_cleanup_entry(dev, q, q->tail, flush);
q->tail = (q->tail + 1) % q->ndesc;
q->queued--;
@@ -360,9 +360,9 @@ mt76_tx_cleanup_queue(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
}
static void *
mt76_rx_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, int *len)
mt76x2_rx_get_buf(struct mt76x2_dev *dev, struct mt76x2_queue *q, int idx, int *len)
{
struct mt76_queue_entry *e;
struct mt76x2_queue_entry *e;
dma_addr_t buf_addr;
void *buf;
int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
@@ -381,7 +381,7 @@ mt76_rx_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, int *len)
}
static void
mt76_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
mt76x2_rx_cleanup(struct mt76x2_dev *dev, struct mt76x2_queue *q)
{
void *buf;
int idx;
@@ -389,11 +389,11 @@ mt76_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
spin_lock_bh(&q->lock);
do {
idx = mt76_dma_dequeue(dev, q, true);
idx = mt76x2_dma_dequeue(dev, q, true);
if (idx < 0)
break;
buf = mt76_rx_get_buf(dev, q, idx, NULL);
buf = mt76x2_rx_get_buf(dev, q, idx, NULL);
kfree(buf);
} while (1);
@@ -401,7 +401,7 @@ mt76_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
}
static int
mt76_init_tx_queue(struct mt76_dev *dev, struct mt76_queue *q,
mt76x2_init_tx_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q,
int idx, int n_desc, bool mcu)
{
int ret;
@@ -409,26 +409,26 @@ mt76_init_tx_queue(struct mt76_dev *dev, struct mt76_queue *q,
q->regs = dev->regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
q->ndesc = n_desc;
ret = mt76_alloc_queue(dev, q);
ret = mt76x2_alloc_queue(dev, q);
if (ret)
return ret;
mt76_irq_enable(dev, MT_INT_TX_DONE(idx));
mt76x2_irq_enable(dev, MT_INT_TX_DONE(idx));
return 0;
}
static void
mt76_process_rx_skb(struct mt76_dev *dev, struct mt76_queue *q,
mt76x2_process_rx_skb(struct mt76x2_dev *dev, struct mt76x2_queue *q,
struct sk_buff *skb, u32 info)
{
void *rxwi = skb->data - sizeof(struct mt76_rxwi);
void *rxwi = skb->data - sizeof(struct mt76x2_rxwi);
if (q == &dev->mcu.q_rx) {
u32 *rxfce;
/* No RXWI header, data starts with payload */
skb_push(skb, sizeof(struct mt76_rxwi));
skb_push(skb, sizeof(struct mt76x2_rxwi));
rxfce = (u32 *) skb->cb;
*rxfce = info;
@@ -438,29 +438,29 @@ mt76_process_rx_skb(struct mt76_dev *dev, struct mt76_queue *q,
return;
}
if (mt76_mac_process_rx(dev, skb, rxwi)) {
if (mt76x2_mac_process_rx(dev, skb, rxwi)) {
dev_kfree_skb(skb);
return;
}
mt76_rx(dev, skb);
mt76x2_rx(dev, skb);
}
static int
mt76_process_rx_queue(struct mt76_dev *dev, struct mt76_queue *q, int budget)
mt76x2_process_rx_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q, int budget)
{
struct mt76_desc *desc;
struct mt76x2_desc *desc;
struct sk_buff *skb;
unsigned char *data;
int idx, len;
int done = 0;
while (done < budget) {
idx = mt76_dma_dequeue(dev, q, false);
idx = mt76x2_dma_dequeue(dev, q, false);
if (idx < 0)
break;
data = mt76_rx_get_buf(dev, q, idx, &len);
data = mt76x2_rx_get_buf(dev, q, idx, &len);
skb = build_skb(data, 0);
if (!skb) {
kfree(data);
@@ -476,16 +476,16 @@ mt76_process_rx_queue(struct mt76_dev *dev, struct mt76_queue *q, int budget)
__skb_put(skb, len);
desc = &q->desc[idx];
mt76_process_rx_skb(dev, q, skb, le32_to_cpu(desc->info));
mt76x2_process_rx_skb(dev, q, skb, le32_to_cpu(desc->info));
done++;
}
mt76_dma_rx_fill(dev, q);
mt76x2_dma_rx_fill(dev, q);
return done;
}
static int
mt76_init_rx_queue(struct mt76_dev *dev, struct mt76_queue *q,
mt76x2_init_rx_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q,
int idx, int n_desc, int bufsize)
{
int ret;
@@ -494,64 +494,64 @@ mt76_init_rx_queue(struct mt76_dev *dev, struct mt76_queue *q,
q->ndesc = n_desc;
q->buf_size = bufsize;
ret = mt76_alloc_queue(dev, q);
ret = mt76x2_alloc_queue(dev, q);
if (ret)
return ret;
mt76_irq_enable(dev, MT_INT_RX_DONE(idx));
mt76x2_irq_enable(dev, MT_INT_RX_DONE(idx));
return 0;
}
static void
mt76_tx_tasklet(unsigned long data)
mt76x2_tx_tasklet(unsigned long data)
{
struct mt76_dev *dev = (struct mt76_dev *) data;
struct mt76x2_dev *dev = (struct mt76x2_dev *) data;
int i;
mt76_mac_process_tx_status_fifo(dev);
mt76x2_mac_process_tx_status_fifo(dev);
for (i = ARRAY_SIZE(dev->q_tx) - 1; i >= 0; i--)
mt76_tx_cleanup_queue(dev, &dev->q_tx[i], false);
mt76x2_tx_cleanup_queue(dev, &dev->q_tx[i], false);
mt76_mac_poll_tx_status(dev, false);
mt76_irq_enable(dev, MT_INT_TX_DONE_ALL);
mt76x2_mac_poll_tx_status(dev, false);
mt76x2_irq_enable(dev, MT_INT_TX_DONE_ALL);
}
static int
mt76_dma_rx_poll(struct napi_struct *napi, int budget)
mt76x2_dma_rx_poll(struct napi_struct *napi, int budget)
{
struct mt76_dev *dev = container_of(napi, struct mt76_dev, napi);
struct mt76x2_dev *dev = container_of(napi, struct mt76x2_dev, napi);
int done;
done = mt76_process_rx_queue(dev, &dev->q_rx, budget);
done = mt76x2_process_rx_queue(dev, &dev->q_rx, budget);
if (done < budget) {
napi_complete(napi);
mt76_irq_enable(dev, MT_INT_RX_DONE(0));
mt76x2_irq_enable(dev, MT_INT_RX_DONE(0));
}
return done;
}
static void
mt76_rx_tasklet(unsigned long data)
mt76x2_rx_tasklet(unsigned long data)
{
struct mt76_dev *dev = (struct mt76_dev *) data;
struct mt76x2_dev *dev = (struct mt76x2_dev *) data;
mt76_process_rx_queue(dev, &dev->mcu.q_rx, dev->mcu.q_rx.ndesc);
mt76x2_process_rx_queue(dev, &dev->mcu.q_rx, dev->mcu.q_rx.ndesc);
mt76_irq_enable(dev, MT_INT_RX_DONE(1));
mt76x2_irq_enable(dev, MT_INT_RX_DONE(1));
}
static const struct mt76_dma_ops mt76x2_dma_ops = {
.queue_skb = mt76_dma_tx_queue_skb,
.queue_mcu = mt76_dma_tx_queue_mcu,
.cleanup_idx = mt76_dma_tx_cleanup_idx,
.add_rx_buf = mt76_dma_add_rx_buf,
static const struct mt76x2_dma_ops mt76x2_dma_ops = {
.queue_skb = mt76x2_dma_tx_queue_skb,
.queue_mcu = mt76x2_dma_tx_queue_mcu,
.cleanup_idx = mt76x2_dma_tx_cleanup_idx,
.add_rx_buf = mt76x2_dma_add_rx_buf,
};
int mt76_dma_init(struct mt76_dev *dev)
int mt76x2_dma_init(struct mt76x2_dev *dev)
{
static const u8 wmm_queue_map[] = {
[IEEE80211_AC_BE] = 0,
@@ -575,59 +575,59 @@ int mt76_dma_init(struct mt76_dev *dev)
}
init_dummy_netdev(&dev->napi_dev);
netif_napi_add(&dev->napi_dev, &dev->napi, mt76_dma_rx_poll, 64);
netif_napi_add(&dev->napi_dev, &dev->napi, mt76x2_dma_rx_poll, 64);
tasklet_init(&dev->tx_tasklet, mt76_tx_tasklet, (unsigned long) dev);
tasklet_init(&dev->rx_tasklet, mt76_rx_tasklet, (unsigned long) dev);
tasklet_init(&dev->tx_tasklet, mt76x2_tx_tasklet, (unsigned long) dev);
tasklet_init(&dev->rx_tasklet, mt76x2_rx_tasklet, (unsigned long) dev);
mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
mt76x2_wr(dev, MT_WPDMA_RST_IDX, ~0);
for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
ret = mt76_init_tx_queue(dev, &dev->q_tx[i], wmm_queue_map[i],
ret = mt76x2_init_tx_queue(dev, &dev->q_tx[i], wmm_queue_map[i],
MT_TX_RING_SIZE, false);
if (ret)
return ret;
}
ret = mt76_init_tx_queue(dev, &dev->q_tx[MT_TXQ_PSD],
ret = mt76x2_init_tx_queue(dev, &dev->q_tx[MT_TXQ_PSD],
MT_TX_HW_QUEUE_MGMT, MT_TX_RING_SIZE, false);
if (ret)
return ret;
ret = mt76_init_tx_queue(dev, &dev->q_tx[MT_TXQ_MCU],
ret = mt76x2_init_tx_queue(dev, &dev->q_tx[MT_TXQ_MCU],
MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE, true);
if (ret)
return ret;
ret = mt76_init_rx_queue(dev, &dev->mcu.q_rx, 1, MT_MCU_RING_SIZE,
ret = mt76x2_init_rx_queue(dev, &dev->mcu.q_rx, 1, MT_MCU_RING_SIZE,
MT_RX_BUF_SIZE);
if (ret)
return ret;
ret = mt76_init_rx_queue(dev, &dev->q_rx, 0,
ret = mt76x2_init_rx_queue(dev, &dev->q_rx, 0,
MT_RX_RING_SIZE, MT_RX_BUF_SIZE);
if (ret)
return ret;
mt76_dma_rx_fill(dev, &dev->q_rx);
mt76_dma_rx_fill(dev, &dev->mcu.q_rx);
mt76x2_dma_rx_fill(dev, &dev->q_rx);
mt76x2_dma_rx_fill(dev, &dev->mcu.q_rx);
return 0;
}
void mt76_dma_cleanup(struct mt76_dev *dev)
void mt76x2_dma_cleanup(struct mt76x2_dev *dev)
{
struct mt76_txwi_cache *t;
struct mt76x2_txwi_cache *t;
int i;
tasklet_kill(&dev->tx_tasklet);
tasklet_kill(&dev->rx_tasklet);
for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++)
mt76_tx_cleanup_queue(dev, &dev->q_tx[i], true);
mt76_rx_cleanup(dev, &dev->q_rx);
mt76_rx_cleanup(dev, &dev->mcu.q_rx);
mt76x2_tx_cleanup_queue(dev, &dev->q_tx[i], true);
mt76x2_rx_cleanup(dev, &dev->q_rx);
mt76x2_rx_cleanup(dev, &dev->mcu.q_rx);
while ((t = __mt76_get_txwi(dev)) != NULL)
while ((t = __mt76x2_get_txwi(dev)) != NULL)
dma_unmap_single(dev->dev, t->dma_addr, sizeof(t->txwi),
DMA_TO_DEVICE);
}
dma.h
+2 -2
View File
@@ -50,7 +50,7 @@
#define MT_MCU_MSG_TYPE GENMASK(31, 30)
#define MT_MCU_MSG_TYPE_CMD BIT(30)
enum mt76_qsel {
enum mt76x2_qsel {
MT_QSEL_MGMT,
MT_QSEL_HCCA,
MT_QSEL_EDCA,
@@ -67,7 +67,7 @@ enum dma_msg_port {
DISCARD,
};
struct mt76_desc {
struct mt76x2_desc {
__le32 buf0;
__le32 ctrl;
__le32 buf1;
eeprom.c
+118 -118
View File
@@ -20,7 +20,7 @@
#define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1
static int
mt76_eeprom_copy(struct mt76_dev *dev, enum mt76_eeprom_field field,
mt76x2_eeprom_copy(struct mt76x2_dev *dev, enum mt76x2_eeprom_field field,
void *dest, int len)
{
if (field + len > dev->eeprom.size)
@@ -31,7 +31,7 @@ mt76_eeprom_copy(struct mt76_dev *dev, enum mt76_eeprom_field field,
}
static int
mt76_eeprom_get_macaddr(struct mt76_dev *dev)
mt76x2_eeprom_get_macaddr(struct mt76x2_dev *dev)
{
void *src = dev->eeprom.data + MT_EE_MAC_ADDR;
@@ -40,7 +40,7 @@ mt76_eeprom_get_macaddr(struct mt76_dev *dev)
}
static void
mt76_eeprom_parse_hw_cap(struct mt76_dev *dev)
mt76x2_eeprom_parse_hw_cap(struct mt76x2_dev *dev)
{
u16 val = MT_EE_NIC_CONF_0;
@@ -59,31 +59,31 @@ mt76_eeprom_parse_hw_cap(struct mt76_dev *dev)
}
static int
mt76_efuse_read(struct mt76_dev *dev, u16 addr, u8 *data)
mt76x2_efuse_read(struct mt76x2_dev *dev, u16 addr, u8 *data)
{
u32 val;
int i;
val = mt76_rr(dev, MT_EFUSE_CTRL);
val = mt76x2_rr(dev, MT_EFUSE_CTRL);
val &= ~(MT_EFUSE_CTRL_AIN |
MT_EFUSE_CTRL_MODE);
val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf);
val |= MT_EFUSE_CTRL_KICK;
mt76_wr(dev, MT_EFUSE_CTRL, val);
mt76x2_wr(dev, MT_EFUSE_CTRL, val);
if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
if (!mt76x2_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
return -ETIMEDOUT;
udelay(2);
val = mt76_rr(dev, MT_EFUSE_CTRL);
val = mt76x2_rr(dev, MT_EFUSE_CTRL);
if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
memset(data, 0xff, 16);
return 0;
}
for (i = 0; i < 4; i++) {
val = mt76_rr(dev, MT_EFUSE_DATA(i));
val = mt76x2_rr(dev, MT_EFUSE_DATA(i));
put_unaligned_le32(val, data + 4 * i);
}
@@ -91,12 +91,12 @@ mt76_efuse_read(struct mt76_dev *dev, u16 addr, u8 *data)
}
static int
mt76_get_efuse_data(struct mt76_dev *dev, void *buf, int len)
mt76x2_get_efuse_data(struct mt76x2_dev *dev, void *buf, int len)
{
int ret, i;
for (i = 0; i + 16 <= len; i += 16) {
ret = mt76_efuse_read(dev, i, buf + i);
ret = mt76x2_efuse_read(dev, i, buf + i);
if (ret)
return ret;
}
@@ -105,7 +105,7 @@ mt76_get_efuse_data(struct mt76_dev *dev, void *buf, int len)
}
static bool
mt76_has_cal_free_data(struct mt76_dev *dev, u8 *efuse)
mt76x2_has_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
{
if (get_unaligned_le16(efuse + MT_EE_NIC_CONF_0) != 0)
return false;
@@ -130,7 +130,7 @@ mt76_has_cal_free_data(struct mt76_dev *dev, u8 *efuse)
static void
mt76_apply_cal_free_data(struct mt76_dev *dev, u8 *efuse)
mt76x2_apply_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
{
#define GROUP_5G(_id) \
MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
@@ -170,7 +170,7 @@ mt76_apply_cal_free_data(struct mt76_dev *dev, u8 *efuse)
u16 val;
int i;
if (!mt76_has_cal_free_data(dev, efuse))
if (!mt76x2_has_cal_free_data(dev, efuse))
return;
for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
@@ -197,7 +197,7 @@ mt76_apply_cal_free_data(struct mt76_dev *dev, u8 *efuse)
}
static int
mt76_eeprom_load(struct mt76_dev *dev)
mt76x2_eeprom_load(struct mt76x2_dev *dev)
{
void *efuse;
int len = MT7662_EEPROM_SIZE;
@@ -211,15 +211,15 @@ mt76_eeprom_load(struct mt76_dev *dev)
dev->otp.size = len;
dev->otp.data = dev->eeprom.data + len;
found = !mt76_get_of_eeprom(dev, len);
found = !mt76x2_get_of_eeprom(dev, len);
efuse = dev->otp.data;
if (mt76_get_efuse_data(dev, efuse, len))
if (mt76x2_get_efuse_data(dev, efuse, len))
goto out;
if (found) {
mt76_apply_cal_free_data(dev, efuse);
mt76x2_apply_cal_free_data(dev, efuse);
} else {
/* FIXME: check if efuse data is complete */
found = true;
@@ -234,7 +234,7 @@ out:
}
static inline int
mt76_sign_extend(u32 val, unsigned size)
mt76x2_sign_extend(u32 val, unsigned size)
{
bool sign = val & BIT(size - 1);
val &= BIT(size - 1) - 1;
@@ -242,10 +242,10 @@ mt76_sign_extend(u32 val, unsigned size)
}
static inline int
mt76_sign_extend_optional(u32 val, unsigned size)
mt76x2_sign_extend_optional(u32 val, unsigned size)
{
bool enable = val & BIT(size);
return enable ? mt76_sign_extend(val, size) : 0;
return enable ? mt76x2_sign_extend(val, size) : 0;
}
static bool
@@ -255,7 +255,7 @@ field_valid(u8 val)
}
static void
mt76_set_rx_gain_group(struct mt76_dev *dev, u8 val)
mt76x2_set_rx_gain_group(struct mt76x2_dev *dev, u8 val)
{
s8 *dest = dev->cal.rx.high_gain;
@@ -265,12 +265,12 @@ mt76_set_rx_gain_group(struct mt76_dev *dev, u8 val)
return;
}
dest[0] = mt76_sign_extend(val, 4);
dest[1] = mt76_sign_extend(val >> 4, 4);
dest[0] = mt76x2_sign_extend(val, 4);
dest[1] = mt76x2_sign_extend(val >> 4, 4);
}
static void
mt76_set_rssi_offset(struct mt76_dev *dev, int chain, u8 val)
mt76x2_set_rssi_offset(struct mt76x2_dev *dev, int chain, u8 val)
{
s8 *dest = dev->cal.rx.rssi_offset;
@@ -279,11 +279,11 @@ mt76_set_rssi_offset(struct mt76_dev *dev, int chain, u8 val)
return;
}
dest[chain] = mt76_sign_extend(val, 6);
dest[chain] = mt76x2_sign_extend(val, 6);
}
static enum mt76_cal_channel_group
mt76_get_cal_channel_group(int channel)
static enum mt76x2_cal_channel_group
mt76x2_get_cal_channel_group(int channel)
{
if (channel >= 184 && channel <= 196)
return MT_CH_5G_JAPAN;
@@ -299,27 +299,27 @@ mt76_get_cal_channel_group(int channel)
}
static u8
mt76_get_5g_rx_gain(struct mt76_dev *dev, u8 channel)
mt76x2_get_5g_rx_gain(struct mt76x2_dev *dev, u8 channel)
{
enum mt76_cal_channel_group group = mt76_get_cal_channel_group(channel);
enum mt76x2_cal_channel_group group = mt76x2_get_cal_channel_group(channel);
switch (group) {
case MT_CH_5G_JAPAN:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
case MT_CH_5G_UNII_1:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
case MT_CH_5G_UNII_2:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
case MT_CH_5G_UNII_2E_1:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
case MT_CH_5G_UNII_2E_2:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
default:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
}
}
void mt76_read_rx_gain(struct mt76_dev *dev)
void mt76x2_read_rx_gain(struct mt76x2_dev *dev)
{
struct ieee80211_channel *chan = dev->chandef.chan;
int channel = chan->hw_value;
@@ -327,30 +327,30 @@ void mt76_read_rx_gain(struct mt76_dev *dev)
u16 val;
if (chan->band == IEEE80211_BAND_2GHZ)
val = mt76_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
else
val = mt76_get_5g_rx_gain(dev, channel);
val = mt76x2_get_5g_rx_gain(dev, channel);
mt76_set_rx_gain_group(dev, val);
mt76x2_set_rx_gain_group(dev, val);
if (chan->band == IEEE80211_BAND_2GHZ) {
val = mt76_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_0);
mt76_set_rssi_offset(dev, 0, val);
mt76_set_rssi_offset(dev, 1, val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_0);
mt76x2_set_rssi_offset(dev, 0, val);
mt76x2_set_rssi_offset(dev, 1, val >> 8);
} else {
val = mt76_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_0);
mt76_set_rssi_offset(dev, 0, val);
mt76_set_rssi_offset(dev, 1, val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_0);
mt76x2_set_rssi_offset(dev, 0, val);
mt76x2_set_rssi_offset(dev, 1, val >> 8);
}
val = mt76_eeprom_get(dev, MT_EE_LNA_GAIN);
val = mt76x2_eeprom_get(dev, MT_EE_LNA_GAIN);
lna_2g = val & 0xff;
lna_5g[0] = val >> 8;
val = mt76_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_1);
val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_1);
lna_5g[1] = val >> 8;
val = mt76_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_1);
val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_1);
lna_5g[2] = val >> 8;
if (!field_valid(lna_5g[1]))
@@ -364,7 +364,7 @@ void mt76_read_rx_gain(struct mt76_dev *dev)
dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_1);
val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
if (val & MT_EE_NIC_CONF_1_LNA_EXT_2G)
lna_2g = 0;
if (val & MT_EE_NIC_CONF_1_LNA_EXT_5G)
@@ -382,15 +382,15 @@ void mt76_read_rx_gain(struct mt76_dev *dev)
}
static s8
mt76_rate_power_val(u8 val)
mt76x2_rate_power_val(u8 val)
{
if (!field_valid(val))
return 0;
return mt76_sign_extend_optional(val, 7);
return mt76x2_sign_extend_optional(val, 7);
}
void mt76_get_rate_power(struct mt76_dev *dev, struct mt76_rate_power *t)
void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76x2_rate_power *t)
{
bool is_5ghz = false;
u16 val;
@@ -399,56 +399,56 @@ void mt76_get_rate_power(struct mt76_dev *dev, struct mt76_rate_power *t)
memset(t, 0, sizeof(*t));
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_CCK);
t->cck[0] = t->cck[1] = mt76_rate_power_val(val);
t->cck[2] = t->cck[3] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_CCK);
t->cck[0] = t->cck[1] = mt76x2_rate_power_val(val);
t->cck[2] = t->cck[3] = mt76x2_rate_power_val(val >> 8);
if (is_5ghz)
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
else
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
t->ofdm[0] = t->ofdm[1] = mt76_rate_power_val(val);
t->ofdm[2] = t->ofdm[3] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
t->ofdm[0] = t->ofdm[1] = mt76x2_rate_power_val(val);
t->ofdm[2] = t->ofdm[3] = mt76x2_rate_power_val(val >> 8);
if (is_5ghz)
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
else
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
t->ofdm[4] = t->ofdm[5] = mt76_rate_power_val(val);
t->ofdm[6] = t->ofdm[7] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
t->ofdm[4] = t->ofdm[5] = mt76x2_rate_power_val(val);
t->ofdm[6] = t->ofdm[7] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
t->ht[0] = t->ht[1] = mt76_rate_power_val(val);
t->ht[2] = t->ht[3] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
t->ht[0] = t->ht[1] = mt76x2_rate_power_val(val);
t->ht[2] = t->ht[3] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
t->ht[4] = t->ht[5] = mt76_rate_power_val(val);
t->ht[6] = t->ht[7] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
t->ht[4] = t->ht[5] = mt76x2_rate_power_val(val);
t->ht[6] = t->ht[7] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
t->ht[8] = t->ht[9] = mt76_rate_power_val(val);
t->ht[10] = t->ht[11] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
t->ht[8] = t->ht[9] = mt76x2_rate_power_val(val);
t->ht[10] = t->ht[11] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
t->ht[12] = t->ht[13] = mt76_rate_power_val(val);
t->ht[14] = t->ht[15] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
t->ht[12] = t->ht[13] = mt76x2_rate_power_val(val);
t->ht[14] = t->ht[15] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0);
t->vht[0] = t->vht[1] = mt76_rate_power_val(val);
t->vht[2] = t->vht[3] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0);
t->vht[0] = t->vht[1] = mt76x2_rate_power_val(val);
t->vht[2] = t->vht[3] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4);
t->vht[4] = t->vht[5] = mt76_rate_power_val(val);
t->vht[6] = t->vht[7] = mt76_rate_power_val(val >> 8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4);
t->vht[4] = t->vht[5] = mt76x2_rate_power_val(val);
t->vht[6] = t->vht[7] = mt76x2_rate_power_val(val >> 8);
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
if (!is_5ghz)
val >>= 8;
t->vht[8] = t->vht[9] = mt76_rate_power_val(val >> 8);
t->vht[8] = t->vht[9] = mt76x2_rate_power_val(val >> 8);
}
static void
mt76_get_power_info_2g(struct mt76_dev *dev, struct mt76_tx_power_info *t,
mt76x2_get_power_info_2g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
int chain, int offset)
{
int channel = dev->chandef.chan->hw_value;
@@ -463,23 +463,23 @@ mt76_get_power_info_2g(struct mt76_dev *dev, struct mt76_tx_power_info *t,
else
delta_idx = 5;
mt76_eeprom_copy(dev, offset, data, sizeof(data));
mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
t->chain[chain].tssi_slope = data[0];
t->chain[chain].tssi_offset = data[1];
t->chain[chain].target_power = data[2];
t->chain[chain].delta = mt76_sign_extend_optional(data[delta_idx], 7);
t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
val = mt76_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
t->target_power = val >> 8;
}
static void
mt76_get_power_info_5g(struct mt76_dev *dev, struct mt76_tx_power_info *t,
mt76x2_get_power_info_5g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
int chain, int offset)
{
int channel = dev->chandef.chan->hw_value;
enum mt76_cal_channel_group group = mt76_get_cal_channel_group(channel);
enum mt76x2_cal_channel_group group = mt76x2_get_cal_channel_group(channel);
int delta_idx;
u16 val;
u8 data[5];
@@ -511,42 +511,42 @@ mt76_get_power_info_5g(struct mt76_dev *dev, struct mt76_tx_power_info *t,
else
delta_idx = 4;
mt76_eeprom_copy(dev, offset, data, sizeof(data));
mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
t->chain[chain].tssi_slope = data[0];
t->chain[chain].tssi_offset = data[1];
t->chain[chain].target_power = data[2];
t->chain[chain].delta = mt76_sign_extend_optional(data[delta_idx], 7);
t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
val = mt76_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
t->target_power = val & 0xff;
}
void mt76_get_power_info(struct mt76_dev *dev, struct mt76_tx_power_info *t)
void mt76x2_get_power_info(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t)
{
u16 bw40, bw80;
memset(t, 0, sizeof(*t));
bw40 = mt76_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
bw80 = mt76_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
bw40 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
bw80 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
if (dev->chandef.chan->band == IEEE80211_BAND_5GHZ) {
bw40 >>= 8;
mt76_get_power_info_5g(dev, t, 0, MT_EE_TX_POWER_0_START_5G);
mt76_get_power_info_5g(dev, t, 1, MT_EE_TX_POWER_1_START_5G);
mt76x2_get_power_info_5g(dev, t, 0, MT_EE_TX_POWER_0_START_5G);
mt76x2_get_power_info_5g(dev, t, 1, MT_EE_TX_POWER_1_START_5G);
} else {
mt76_get_power_info_2g(dev, t, 0, MT_EE_TX_POWER_0_START_2G);
mt76_get_power_info_2g(dev, t, 1, MT_EE_TX_POWER_1_START_2G);
mt76x2_get_power_info_2g(dev, t, 0, MT_EE_TX_POWER_0_START_2G);
mt76x2_get_power_info_2g(dev, t, 1, MT_EE_TX_POWER_1_START_2G);
}
if (mt76_tssi_enabled(dev) || !field_valid(t->target_power))
if (mt76x2_tssi_enabled(dev) || !field_valid(t->target_power))
t->target_power = t->chain[0].target_power;
t->delta_bw40 = mt76_rate_power_val(bw40);
t->delta_bw80 = mt76_rate_power_val(bw80);
t->delta_bw40 = mt76x2_rate_power_val(bw40);
t->delta_bw80 = mt76x2_rate_power_val(bw80);
}
int mt76_get_temp_comp(struct mt76_dev *dev, struct mt76_temp_comp *t)
int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t)
{
enum ieee80211_band band = dev->chandef.chan->band;
u16 val, slope;
@@ -554,24 +554,24 @@ int mt76_get_temp_comp(struct mt76_dev *dev, struct mt76_temp_comp *t)
memset(t, 0, sizeof(*t));
val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_1);
val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
if (!(val & MT_EE_NIC_CONF_1_TEMP_TX_ALC))
return -EINVAL;
if (!mt76_ext_pa_enabled(dev, band))
if (!mt76x2_ext_pa_enabled(dev, band))
return -EINVAL;
val = mt76_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
if (!(val & BIT(7)))
return -EINVAL;
t->temp_25_ref = val & 0x7f;
if (band == IEEE80211_BAND_5GHZ) {
slope = mt76_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
bounds = mt76_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
} else {
slope = mt76_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
bounds = mt76_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80) >> 8;
slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80) >> 8;
}
t->high_slope = slope & 0xff;
@@ -582,9 +582,9 @@ int mt76_get_temp_comp(struct mt76_dev *dev, struct mt76_temp_comp *t)
return 0;
}
bool mt76_ext_pa_enabled(struct mt76_dev *dev, enum ieee80211_band band)
bool mt76x2_ext_pa_enabled(struct mt76x2_dev *dev, enum ieee80211_band band)
{
u16 conf1 = mt76_eeprom_get(dev, MT_EE_NIC_CONF_0);
u16 conf1 = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0);
if (band == IEEE80211_BAND_5GHZ)
return !(conf1 & MT_EE_NIC_CONF_0_PA_INT_5G);
@@ -592,18 +592,18 @@ bool mt76_ext_pa_enabled(struct mt76_dev *dev, enum ieee80211_band band)
return !(conf1 & MT_EE_NIC_CONF_0_PA_INT_2G);
}
int mt76_eeprom_init(struct mt76_dev *dev)
int mt76x2_eeprom_init(struct mt76x2_dev *dev)
{
int ret;
ret = mt76_eeprom_load(dev);
ret = mt76x2_eeprom_load(dev);
if (ret)
return ret;
mt76_eeprom_parse_hw_cap(dev);
mt76_get_of_overrides(dev);
mt76x2_eeprom_parse_hw_cap(dev);
mt76x2_get_of_overrides(dev);
mt76_eeprom_get_macaddr(dev);
mt76x2_eeprom_get_macaddr(dev);
if (!is_valid_ether_addr(dev->macaddr)) {
eth_random_addr(dev->macaddr);
dev_printk(KERN_INFO, dev->dev,
eeprom.h
+18 -18
View File
@@ -16,7 +16,7 @@
#include "mt76.h"
enum mt76_eeprom_field {
enum mt76x2_eeprom_field {
MT_EE_CHIP_ID = 0x000,
MT_EE_VERSION = 0x002,
MT_EE_MAC_ADDR = 0x004,
@@ -97,12 +97,12 @@ enum mt76_eeprom_field {
#define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
enum mt76_board_type {
enum mt76x2_board_type {
BOARD_TYPE_2GHZ = 1,
BOARD_TYPE_5GHZ = 2,
};
enum mt76_cal_channel_group {
enum mt76x2_cal_channel_group {
MT_CH_5G_JAPAN,
MT_CH_5G_UNII_1,
MT_CH_5G_UNII_2,
@@ -112,7 +112,7 @@ enum mt76_cal_channel_group {
__MT_CH_MAX
};
struct mt76_tx_power_info {
struct mt76x2_tx_power_info {
u8 target_power;
s8 delta_bw40;
@@ -126,7 +126,7 @@ struct mt76_tx_power_info {
} chain[MT_MAX_CHAINS];
};
struct mt76_temp_comp {
struct mt76x2_temp_comp {
u8 temp_25_ref;
int lower_bound; /* J */
int upper_bound; /* J */
@@ -135,7 +135,7 @@ struct mt76_temp_comp {
};
static inline int
mt76_eeprom_get(struct mt76_dev *dev, enum mt76_eeprom_field field)
mt76x2_eeprom_get(struct mt76x2_dev *dev, enum mt76x2_eeprom_field field)
{
if ((field & 1) || field >= __MT_EE_MAX)
return -1;
@@ -143,32 +143,32 @@ mt76_eeprom_get(struct mt76_dev *dev, enum mt76_eeprom_field field)
return get_unaligned_le16(dev->eeprom.data + field);
}
void mt76_get_rate_power(struct mt76_dev *dev, struct mt76_rate_power *t);
void mt76_get_power_info(struct mt76_dev *dev, struct mt76_tx_power_info *t);
int mt76_get_temp_comp(struct mt76_dev *dev, struct mt76_temp_comp *t);
bool mt76_ext_pa_enabled(struct mt76_dev *dev, enum ieee80211_band band);
void mt76_read_rx_gain(struct mt76_dev *dev);
void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76x2_rate_power *t);
void mt76x2_get_power_info(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t);
int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t);
bool mt76x2_ext_pa_enabled(struct mt76x2_dev *dev, enum ieee80211_band band);
void mt76x2_read_rx_gain(struct mt76x2_dev *dev);
static inline bool
mt76_temp_tx_alc_enabled(struct mt76_dev *dev)
mt76x2_temp_tx_alc_enabled(struct mt76x2_dev *dev)
{
return mt76_eeprom_get(dev, MT_EE_NIC_CONF_1) &
return mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) &
MT_EE_NIC_CONF_1_TEMP_TX_ALC;
}
static inline bool
mt76_tssi_enabled(struct mt76_dev *dev)
mt76x2_tssi_enabled(struct mt76x2_dev *dev)
{
return !mt76_temp_tx_alc_enabled(dev) &&
(mt76_eeprom_get(dev, MT_EE_NIC_CONF_1) &
return !mt76x2_temp_tx_alc_enabled(dev) &&
(mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) &
MT_EE_NIC_CONF_1_TX_ALC_EN);
}
static inline bool
mt76_has_ext_lna(struct mt76_dev *dev)
mt76x2_has_ext_lna(struct mt76x2_dev *dev)
{
u32 val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_1);
u32 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
if (dev->chandef.chan->band == IEEE80211_BAND_2GHZ)
return val & MT_EE_NIC_CONF_1_LNA_EXT_2G;
init.c
+161 -161
View File
@@ -17,12 +17,12 @@
#include "mcu.h"
static bool
mt76_wait_for_mac(struct mt76_dev *dev)
mt76x2_wait_for_mac(struct mt76x2_dev *dev)
{
int i;
for (i = 0; i < 500; i++) {
switch (mt76_rr(dev, MT_MAC_CSR0)) {
switch (mt76x2_rr(dev, MT_MAC_CSR0)) {
case 0:
case ~0:
break;
@@ -36,16 +36,16 @@ mt76_wait_for_mac(struct mt76_dev *dev)
}
static bool
wait_for_wpdma(struct mt76_dev *dev)
wait_for_wpdma(struct mt76x2_dev *dev)
{
return mt76_poll(dev, MT_WPDMA_GLO_CFG,
return mt76x2_poll(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
0, 1000);
}
static void
mt76_mac_pbf_init(struct mt76_dev *dev)
mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
{
u32 val;
@@ -55,17 +55,17 @@ mt76_mac_pbf_init(struct mt76_dev *dev)
MT_PBF_SYS_CTRL_PBF_RESET |
MT_PBF_SYS_CTRL_ASY_RESET;
mt76_set(dev, MT_PBF_SYS_CTRL, val);
mt76_clear(dev, MT_PBF_SYS_CTRL, val);
mt76x2_set(dev, MT_PBF_SYS_CTRL, val);
mt76x2_clear(dev, MT_PBF_SYS_CTRL, val);
mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
mt76x2_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
mt76x2_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
}
static void
mt76_write_mac_initvals(struct mt76_dev *dev)
mt76x2_write_mac_initvals(struct mt76x2_dev *dev)
{
static const struct mt76_reg_pair vals[] = {
static const struct mt76x2_reg_pair vals[] = {
/* Copied from MediaTek reference source */
{ MT_PBF_SYS_CTRL, 0x00080c00 },
{ MT_PBF_CFG, 0x1efebcff },
@@ -122,16 +122,16 @@ mt76_write_mac_initvals(struct mt76_dev *dev)
{ MT_HT_CTRL_CFG, 0x000001ff },
};
mt76_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
mt76x2_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
}
static void
mt76_fixup_xtal(struct mt76_dev *dev)
mt76x2_fixup_xtal(struct mt76x2_dev *dev)
{
u16 eep_val;
s8 offset = 0;
eep_val = mt76_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
offset = eep_val & 0x7f;
if ((eep_val & 0xff) == 0xff)
@@ -141,7 +141,7 @@ mt76_fixup_xtal(struct mt76_dev *dev)
eep_val >>= 8;
if (eep_val == 0x00 || eep_val == 0xff) {
eep_val = mt76_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
eep_val &= 0xff;
if (eep_val == 0x00 || eep_val == 0xff)
@@ -149,16 +149,16 @@ mt76_fixup_xtal(struct mt76_dev *dev)
}
eep_val &= 0x7f;
mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
mt76x2_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
mt76x2_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
eep_val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_2);
eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
switch (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
case 0:
mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
mt76x2_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
break;
case 1:
mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
mt76x2_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
break;
default:
break;
@@ -166,7 +166,7 @@ mt76_fixup_xtal(struct mt76_dev *dev)
}
static void
mt76_init_beacon_offsets(struct mt76_dev *dev)
mt76x2_init_beacon_offsets(struct mt76x2_dev *dev)
{
u16 base = MT_BEACON_BASE;
u32 regs[4] = {};
@@ -179,19 +179,19 @@ mt76_init_beacon_offsets(struct mt76_dev *dev)
}
for (i = 0; i < 4; i++)
mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
mt76x2_wr(dev, MT_BCN_OFFSET(i), regs[i]);
}
int mt76_mac_reset(struct mt76_dev *dev, bool hard)
int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
{
static const u8 null_addr[ETH_ALEN] = {};
u32 val;
int i, k;
if (!mt76_wait_for_mac(dev))
if (!mt76x2_wait_for_mac(dev))
return -ETIMEDOUT;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val = mt76x2_rr(dev, MT_WPDMA_GLO_CFG);
val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
@@ -200,121 +200,121 @@ int mt76_mac_reset(struct mt76_dev *dev, bool hard)
MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76x2_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76_mac_pbf_init(dev);
mt76_write_mac_initvals(dev);
mt76_fixup_xtal(dev);
mt76x2_mac_pbf_init(dev);
mt76x2_write_mac_initvals(dev);
mt76x2_fixup_xtal(dev);
mt76_clear(dev, MT_MAC_SYS_CTRL,
mt76x2_clear(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_RESET_CSR |
MT_MAC_SYS_CTRL_RESET_BBP);
if (is_mt7612(dev))
mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
mt76x2_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
mt76x2_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
mt76x2_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
mt76x2_wr(dev, MT_RF_BYPASS_0, 0x06000000);
mt76x2_wr(dev, MT_RF_SETTING_0, 0x08800000);
msleep(5);
mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
mt76x2_wr(dev, MT_RF_BYPASS_0, 0x00000000);
mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
mt76x2_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
mt76x2_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
mt76x2_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
mt76x2_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4));
mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr));
mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) |
mt76x2_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr));
mt76x2_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) |
MT76_SET(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
/* Fire a pre-TBTT interrupt 8 ms before TBTT */
mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
mt76x2_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
8 << 4);
mt76_wr(dev, MT_INT_TIMER_EN, 0);
mt76x2_wr(dev, MT_INT_TIMER_EN, 0);
mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
mt76x2_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
if (!hard)
return 0;
for (i = 0; i < 256; i++)
mt76_mac_wcid_setup(dev, i, 0, NULL);
mt76x2_mac_wcid_setup(dev, i, 0, NULL);
for (i = 0; i < 16; i++)
for (k = 0; k < 4; k++)
mt76_mac_shared_key_setup(dev, i, k, NULL);
mt76x2_mac_shared_key_setup(dev, i, k, NULL);
for (i = 0; i < 8; i++) {
mt76_mac_set_bssid(dev, i, null_addr);
mt76_mac_set_beacon(dev, i, NULL);
mt76x2_mac_set_bssid(dev, i, null_addr);
mt76x2_mac_set_beacon(dev, i, NULL);
}
for (i = 0; i < 16; i++)
mt76_rr(dev, MT_TX_STAT_FIFO);
mt76x2_rr(dev, MT_TX_STAT_FIFO);
mt76_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76_init_beacon_offsets(dev);
mt76x2_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN);
mt76x2_init_beacon_offsets(dev);
mt76_set_tx_ackto(dev);
mt76x2_set_tx_ackto(dev);
return 0;
}
int mt76_mac_start(struct mt76_dev *dev)
int mt76x2_mac_start(struct mt76x2_dev *dev)
{
int i;
for (i = 0; i < 16; i++)
mt76_rr(dev, MT_TX_AGG_CNT(i));
mt76x2_rr(dev, MT_TX_AGG_CNT(i));
for (i = 0; i < 16; i++)
mt76_rr(dev, MT_TX_STAT_FIFO);
mt76x2_rr(dev, MT_TX_STAT_FIFO);
memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
mt76x2_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
wait_for_wpdma(dev);
udelay(50);
mt76_set(dev, MT_WPDMA_GLO_CFG,
mt76x2_set(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_EN);
mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
mt76x2_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
mt76x2_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
mt76_wr(dev, MT_MAC_SYS_CTRL,
mt76x2_wr(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_ENABLE_TX |
MT_MAC_SYS_CTRL_ENABLE_RX);
mt76_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | MT_INT_TX_STAT);
mt76x2_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | MT_INT_TX_STAT);
return 0;
}
void mt76_mac_stop(struct mt76_dev *dev, bool force)
void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
{
bool stopped = false;
u32 rts_cfg;
int i;
mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
mt76x2_wr(dev, MT_MAC_SYS_CTRL, 0);
rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
rts_cfg = mt76x2_rr(dev, MT_TX_RTS_CFG);
mt76x2_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
/* Wait for MAC to become idle */
for (i = 0; i < 300; i++) {
if (mt76_rr(dev, MT_MAC_STATUS) &
if (mt76x2_rr(dev, MT_MAC_STATUS) &
(MT_MAC_STATUS_RX | MT_MAC_STATUS_TX))
continue;
if (mt76_rr(dev, MT_BBP(IBI, 12)))
if (mt76x2_rr(dev, MT_BBP(IBI, 12)))
continue;
stopped = true;
@@ -322,121 +322,121 @@ void mt76_mac_stop(struct mt76_dev *dev, bool force)
}
if (force && !stopped) {
mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76x2_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76x2_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
mt76x2_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76x2_clear(dev, MT_BBP(CORE, 4), BIT(0));
}
mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
mt76x2_wr(dev, MT_TX_RTS_CFG, rts_cfg);
}
void mt76_mac_resume(struct mt76_dev *dev)
void mt76x2_mac_resume(struct mt76x2_dev *dev)
{
mt76_wr(dev, MT_MAC_SYS_CTRL,
mt76x2_wr(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_ENABLE_TX |
MT_MAC_SYS_CTRL_ENABLE_RX);
}
static void
mt76_power_on_rf_patch(struct mt76_dev *dev)
mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
{
mt76_set(dev, 0x10130, BIT(0) | BIT(16));
mt76x2_set(dev, 0x10130, BIT(0) | BIT(16));
udelay(1);
mt76_clear(dev, 0x1001c, 0xff);
mt76_set(dev, 0x1001c, 0x30);
mt76x2_clear(dev, 0x1001c, 0xff);
mt76x2_set(dev, 0x1001c, 0x30);
mt76_wr(dev, 0x10014, 0x484f);
mt76x2_wr(dev, 0x10014, 0x484f);
udelay(1);
mt76_set(dev, 0x10130, BIT(17));
mt76x2_set(dev, 0x10130, BIT(17));
udelay(125);
mt76_clear(dev, 0x10130, BIT(16));
mt76x2_clear(dev, 0x10130, BIT(16));
udelay(50);
mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
mt76x2_set(dev, 0x1014c, BIT(19) | BIT(20));
}
static void
mt76_power_on_rf(struct mt76_dev *dev, int unit)
mt76x2_power_on_rf(struct mt76x2_dev *dev, int unit)
{
int shift = unit ? 8 : 0;
/* Enable RF BG */
mt76_set(dev, 0x10130, BIT(0) << shift);
mt76x2_set(dev, 0x10130, BIT(0) << shift);
udelay(10);
/* Enable RFDIG LDO/AFE/ABB/ADDA */
mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
mt76x2_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
udelay(10);
/* Switch RFDIG power to internal LDO */
mt76_clear(dev, 0x10130, BIT(2) << shift);
mt76x2_clear(dev, 0x10130, BIT(2) << shift);
udelay(10);
mt76_power_on_rf_patch(dev);
mt76x2_power_on_rf_patch(dev);
mt76_set(dev, 0x530, 0xf);
mt76x2_set(dev, 0x530, 0xf);
}
static void
mt76_power_on(struct mt76_dev *dev)
mt76x2_power_on(struct mt76x2_dev *dev)
{
u32 val;
/* Turn on WL MTCMOS */
mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
mt76x2_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
val = MT_WLAN_MTC_CTRL_STATE_UP |
MT_WLAN_MTC_CTRL_PWR_ACK |
MT_WLAN_MTC_CTRL_PWR_ACK_S;
mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
mt76x2_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
udelay(10);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
udelay(10);
mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
mt76x2_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
mt76x2_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
/* Turn on AD/DA power down */
mt76_clear(dev, 0x11204, BIT(3));
mt76x2_clear(dev, 0x11204, BIT(3));
/* WLAN function enable */
mt76_set(dev, 0x10080, BIT(0));
mt76x2_set(dev, 0x10080, BIT(0));
/* Release BBP software reset */
mt76_clear(dev, 0x10064, BIT(18));
mt76x2_clear(dev, 0x10064, BIT(18));
mt76_power_on_rf(dev, 0);
mt76_power_on_rf(dev, 1);
mt76x2_power_on_rf(dev, 0);
mt76x2_power_on_rf(dev, 1);
}
void mt76_set_tx_ackto(struct mt76_dev *dev)
void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
{
u8 ackto, sifs, slottime = dev->slottime;
slottime += 3 * dev->coverage_class;
sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
sifs = mt76x2_get_field(dev, MT_XIFS_TIME_CFG,
MT_XIFS_TIME_CFG_OFDM_SIFS);
ackto = slottime + sifs;
mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
mt76x2_rmw_field(dev, MT_TX_TIMEOUT_CFG,
MT_TX_TIMEOUT_CFG_ACKTO, ackto);
}
static void
mt76_set_wlan_state(struct mt76_dev *dev, bool enable)
mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
{
u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
u32 val = mt76x2_rr(dev, MT_WLAN_FUN_CTRL);
if (enable)
val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
@@ -445,34 +445,34 @@ mt76_set_wlan_state(struct mt76_dev *dev, bool enable)
val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
udelay(20);
}
static void
mt76_reset_wlan(struct mt76_dev *dev, bool enable)
mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable)
{
u32 val;
val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
val = mt76x2_rr(dev, MT_WLAN_FUN_CTRL);
val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
udelay(20);
val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
}
mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
mt76x2_wr(dev, MT_WLAN_FUN_CTRL, val);
udelay(20);
mt76_set_wlan_state(dev, enable);
mt76x2_set_wlan_state(dev, enable);
}
int mt76_init_hardware(struct mt76_dev *dev)
int mt76x2_init_hardware(struct mt76x2_dev *dev)
{
static const u16 beacon_offsets[16] = {
/* 1024 byte per beacon */
@@ -499,71 +499,71 @@ int mt76_init_hardware(struct mt76_dev *dev)
int ret;
dev->beacon_offsets = beacon_offsets;
tasklet_init(&dev->pre_tbtt_tasklet, mt76_pre_tbtt_tasklet,
tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
(unsigned long) dev);
dev->chainmask = 0x202;
dev->slottime = 9;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val = mt76x2_rr(dev, MT_WPDMA_GLO_CFG);
val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
MT_WPDMA_GLO_CFG_BIG_ENDIAN |
MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76x2_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76_reset_wlan(dev, true);
mt76_power_on(dev);
mt76x2_reset_wlan(dev, true);
mt76x2_power_on(dev);
ret = mt76_eeprom_init(dev);
ret = mt76x2_eeprom_init(dev);
if (ret)
return ret;
ret = mt76_mac_reset(dev, true);
ret = mt76x2_mac_reset(dev, true);
if (ret)
return ret;
ret = mt76_dma_init(dev);
ret = mt76x2_dma_init(dev);
if (ret)
return ret;
set_bit(MT76_STATE_INITIALIZED, &dev->state);
ret = mt76_mac_start(dev);
ret = mt76x2_mac_start(dev);
if (ret)
return ret;
ret = mt76_mcu_init(dev);
ret = mt76x2_mcu_init(dev);
if (ret)
return ret;
mt76_mac_stop(dev, false);
dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
mt76x2_mac_stop(dev, false);
dev->rxfilter = mt76x2_rr(dev, MT_RX_FILTR_CFG);
return 0;
}
void mt76_stop_hardware(struct mt76_dev *dev)
void mt76x2_stop_hardware(struct mt76x2_dev *dev)
{
cancel_delayed_work_sync(&dev->cal_work);
cancel_delayed_work_sync(&dev->mac_work);
mt76_mcu_set_radio_state(dev, false);
mt76_mac_stop(dev, false);
mt76x2_mcu_set_radio_state(dev, false);
mt76x2_mac_stop(dev, false);
}
void mt76_cleanup(struct mt76_dev *dev)
void mt76x2_cleanup(struct mt76x2_dev *dev)
{
mt76_stop_hardware(dev);
mt76_dma_cleanup(dev);
mt76_mcu_cleanup(dev);
mt76x2_stop_hardware(dev);
mt76x2_dma_cleanup(dev);
mt76x2_mcu_cleanup(dev);
}
struct mt76_dev *mt76_alloc_device(struct device *pdev)
struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
{
struct ieee80211_hw *hw;
struct mt76_dev *dev;
struct mt76x2_dev *dev;
hw = ieee80211_alloc_hw(sizeof(*dev), &mt76_ops);
hw = ieee80211_alloc_hw(sizeof(*dev), &mt76x2_ops);
if (!hw)
return NULL;
@@ -591,7 +591,7 @@ struct mt76_dev *mt76_alloc_device(struct device *pdev)
.max_power = 30, \
}
static const struct ieee80211_channel mt76_channels_2ghz[] = {
static const struct ieee80211_channel mt76x2_channels_2ghz[] = {
CHAN2G(1, 2412),
CHAN2G(2, 2417),
CHAN2G(3, 2422),
@@ -608,7 +608,7 @@ static const struct ieee80211_channel mt76_channels_2ghz[] = {
CHAN2G(14, 2484),
};
static const struct ieee80211_channel mt76_channels_5ghz[] = {
static const struct ieee80211_channel mt76x2_channels_5ghz[] = {
CHAN5G(36, 5180),
CHAN5G(40, 5200),
CHAN5G(44, 5220),
@@ -651,7 +651,7 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
}
static struct ieee80211_rate mt76_rates[] = {
static struct ieee80211_rate mt76x2_rates[] = {
CCK_RATE(0, 10),
CCK_RATE(1, 20),
CCK_RATE(2, 55),
@@ -667,7 +667,7 @@ static struct ieee80211_rate mt76_rates[] = {
};
static int
mt76_init_sband(struct mt76_dev *dev, struct ieee80211_supported_band *sband,
mt76x2_init_sband(struct mt76x2_dev *dev, struct ieee80211_supported_band *sband,
const struct ieee80211_channel *chan, int n_chan,
struct ieee80211_rate *rates, int n_rates)
{
@@ -731,29 +731,29 @@ mt76_init_sband(struct mt76_dev *dev, struct ieee80211_supported_band *sband,
}
static int
mt76_init_sband_2g(struct mt76_dev *dev)
mt76x2_init_sband_2g(struct mt76x2_dev *dev)
{
if (!dev->cap.has_2ghz)
return 0;
dev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &dev->sband_2g;
return mt76_init_sband(dev, &dev->sband_2g,
mt76_channels_2ghz,
ARRAY_SIZE(mt76_channels_2ghz),
mt76_rates, ARRAY_SIZE(mt76_rates));
return mt76x2_init_sband(dev, &dev->sband_2g,
mt76x2_channels_2ghz,
ARRAY_SIZE(mt76x2_channels_2ghz),
mt76x2_rates, ARRAY_SIZE(mt76x2_rates));
}
static int
mt76_init_sband_5g(struct mt76_dev *dev)
mt76x2_init_sband_5g(struct mt76x2_dev *dev)
{
if (!dev->cap.has_5ghz)
return 0;
dev->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &dev->sband_5g;
return mt76_init_sband(dev, &dev->sband_5g,
mt76_channels_5ghz,
ARRAY_SIZE(mt76_channels_5ghz),
mt76_rates + 4, ARRAY_SIZE(mt76_rates) - 4);
return mt76x2_init_sband(dev, &dev->sband_5g,
mt76x2_channels_5ghz,
ARRAY_SIZE(mt76x2_channels_5ghz),
mt76x2_rates + 4, ARRAY_SIZE(mt76x2_rates) - 4);
}
static const struct ieee80211_iface_limit if_limits[] = {
@@ -780,7 +780,7 @@ static const struct ieee80211_iface_combination if_comb[] = {
}
};
int mt76_register_device(struct mt76_dev *dev)
int mt76x2_register_device(struct mt76x2_dev *dev)
{
struct ieee80211_hw *hw = dev->hw;
struct wiphy *wiphy = hw->wiphy;
@@ -788,14 +788,14 @@ int mt76_register_device(struct mt76_dev *dev)
int fifo_size;
int i, ret;
fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76_tx_status));
fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x2_tx_status));
status_fifo = devm_kzalloc(dev->dev, fifo_size, GFP_KERNEL);
if (!status_fifo)
return -ENOMEM;
kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
ret = mt76_init_hardware(dev);
ret = mt76x2_init_hardware(dev);
if (ret)
return ret;
@@ -815,9 +815,9 @@ int mt76_register_device(struct mt76_dev *dev)
ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
hw->sta_data_size = sizeof(struct mt76_sta);
hw->vif_data_size = sizeof(struct mt76_vif);
hw->txq_data_size = sizeof(struct mt76_txq);
hw->sta_data_size = sizeof(struct mt76x2_sta);
hw->vif_data_size = sizeof(struct mt76x2_vif);
hw->txq_data_size = sizeof(struct mt76x2_txq);
dev->macaddr[0] &= ~BIT(1);
SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
@@ -848,28 +848,28 @@ int mt76_register_device(struct mt76_dev *dev)
wiphy->iface_combinations = if_comb;
wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
ret = mt76_init_sband_2g(dev);
ret = mt76x2_init_sband_2g(dev);
if (ret)
goto fail;
ret = mt76_init_sband_5g(dev);
ret = mt76x2_init_sband_5g(dev);
if (ret)
goto fail;
INIT_LIST_HEAD(&dev->txwi_cache);
INIT_DELAYED_WORK(&dev->cal_work, mt76_phy_calibrate);
INIT_DELAYED_WORK(&dev->mac_work, mt76_mac_work);
INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
INIT_DELAYED_WORK(&dev->mac_work, mt76x2_mac_work);
ret = ieee80211_register_hw(hw);
if (ret)
goto fail;
mt76_init_debugfs(dev);
mt76x2_init_debugfs(dev);
return 0;
fail:
mt76_stop_hardware(dev);
mt76x2_stop_hardware(dev);
return ret;
}
mac.c
+84 -84
View File
@@ -17,16 +17,16 @@
#include "eeprom.h"
#include "trace.h"
void mt76_mac_set_bssid(struct mt76_dev *dev, u8 idx, const u8 *addr)
void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr)
{
idx &= 7;
mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
mt76x2_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
mt76x2_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
get_unaligned_le16(addr + 4));
}
static void
mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
mt76x2_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
{
u8 idx = MT76_GET(MT_RXWI_RATE_INDEX, rate);
@@ -92,7 +92,7 @@ mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate)
}
static __le16
mt76_mac_tx_rate_val(struct mt76_dev *dev, const struct ieee80211_tx_rate *rate,
mt76x2_mac_tx_rate_val(struct mt76x2_dev *dev, const struct ieee80211_tx_rate *rate,
u8 *nss_val)
{
u16 rateval;
@@ -142,19 +142,19 @@ mt76_mac_tx_rate_val(struct mt76_dev *dev, const struct ieee80211_tx_rate *rate,
return cpu_to_le16(rateval);
}
void mt76_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid,
void mt76x2_mac_wcid_set_rate(struct mt76x2_dev *dev, struct mt76x2_wcid *wcid,
const struct ieee80211_tx_rate *rate)
{
unsigned long flags;
spin_lock_irqsave(&dev->lock, flags);
wcid->tx_rate = mt76_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
wcid->tx_rate = mt76x2_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
wcid->tx_rate_set = true;
spin_unlock_irqrestore(&dev->lock, flags);
}
void mt76_mac_write_txwi(struct mt76_dev *dev, struct mt76_txwi *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
struct sk_buff *skb, struct mt76x2_wcid *wcid,
struct ieee80211_sta *sta)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -178,7 +178,7 @@ void mt76_mac_write_txwi(struct mt76_dev *dev, struct mt76_txwi *txwi,
txwi->rate = wcid->tx_rate;
nss = wcid->tx_rate_nss;
} else {
txwi->rate = mt76_mac_tx_rate_val(dev, rate, &nss);
txwi->rate = mt76x2_mac_tx_rate_val(dev, rate, &nss);
}
spin_unlock_irqrestore(&dev->lock, flags);
@@ -215,16 +215,16 @@ void mt76_mac_write_txwi(struct mt76_dev *dev, struct mt76_txwi *txwi,
txwi->len_ctl = cpu_to_le16(skb->len);
}
int mt76_mac_process_rx(struct mt76_dev *dev, struct sk_buff *skb, void *rxi)
int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb, void *rxi)
{
struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
struct mt76_rxwi *rxwi = rxi;
struct mt76x2_rxwi *rxwi = rxi;
u32 ctl = le32_to_cpu(rxwi->ctl);
u16 rate = le16_to_cpu(rxwi->rate);
int len;
if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_L2PAD))
mt76_remove_hdr_pad(skb);
mt76x2_remove_hdr_pad(skb);
if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_DECRYPT)) {
status->flag |= RX_FLAG_DECRYPTED;
@@ -235,19 +235,19 @@ int mt76_mac_process_rx(struct mt76_dev *dev, struct sk_buff *skb, void *rxi)
skb_trim(skb, len);
status->chains = BIT(0) | BIT(1);
status->chain_signal[0] = mt76_phy_get_rssi(dev, rxwi->rssi[0], 0);
status->chain_signal[1] = mt76_phy_get_rssi(dev, rxwi->rssi[1], 1);
status->chain_signal[0] = mt76x2_phy_get_rssi(dev, rxwi->rssi[0], 0);
status->chain_signal[1] = mt76x2_phy_get_rssi(dev, rxwi->rssi[1], 1);
status->signal = max(status->chain_signal[0], status->chain_signal[1]);
status->freq = dev->chandef.chan->center_freq;
status->band = dev->chandef.chan->band;
mt76_mac_process_rate(status, rate);
mt76x2_mac_process_rate(status, rate);
return 0;
}
static void
mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
mt76x2_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
enum ieee80211_band band)
{
u8 idx = MT76_GET(MT_RXWI_RATE_INDEX, rate);
@@ -304,15 +304,15 @@ mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
}
static void
mt76_mac_fill_tx_status(struct mt76_dev *dev, struct ieee80211_tx_info *info,
struct mt76_tx_status *st, int n_frames)
mt76x2_mac_fill_tx_status(struct mt76x2_dev *dev, struct ieee80211_tx_info *info,
struct mt76x2_tx_status *st, int n_frames)
{
struct ieee80211_tx_rate *rate = info->status.rates;
int cur_idx, last_rate;
int i;
last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1);
mt76_mac_process_tx_rate(&rate[last_rate], st->rate,
mt76x2_mac_process_tx_rate(&rate[last_rate], st->rate,
dev->chandef.chan->band);
if (last_rate < IEEE80211_TX_MAX_RATES - 1)
rate[last_rate + 1].idx = -1;
@@ -344,13 +344,13 @@ mt76_mac_fill_tx_status(struct mt76_dev *dev, struct ieee80211_tx_info *info,
}
static void
mt76_send_tx_status(struct mt76_dev *dev, struct mt76_tx_status *stat,
mt76x2_send_tx_status(struct mt76x2_dev *dev, struct mt76x2_tx_status *stat,
u8 *update)
{
struct ieee80211_tx_info info = {};
struct ieee80211_sta *sta = NULL;
struct mt76_wcid *wcid = NULL;
struct mt76_sta *msta = NULL;
struct mt76x2_wcid *wcid = NULL;
struct mt76x2_sta *msta = NULL;
rcu_read_lock();
if (stat->wcid < ARRAY_SIZE(dev->wcid))
@@ -359,7 +359,7 @@ mt76_send_tx_status(struct mt76_dev *dev, struct mt76_tx_status *stat,
if (wcid) {
void *priv;
priv = msta = container_of(wcid, struct mt76_sta, wcid);
priv = msta = container_of(wcid, struct mt76x2_sta, wcid);
sta = container_of(priv, struct ieee80211_sta,
drv_priv);
}
@@ -376,7 +376,7 @@ mt76_send_tx_status(struct mt76_dev *dev, struct mt76_tx_status *stat,
stat->wcid == msta->status.wcid && ++msta->n_frames < 32)
goto out;
mt76_mac_fill_tx_status(dev, &info, &msta->status,
mt76x2_mac_fill_tx_status(dev, &info, &msta->status,
msta->n_frames);
msta->status = *stat;
@@ -387,7 +387,7 @@ mt76_send_tx_status(struct mt76_dev *dev, struct mt76_tx_status *stat,
msta->n_frames = 0;
}
} else {
mt76_mac_fill_tx_status(dev, &info, stat, 1);
mt76x2_mac_fill_tx_status(dev, &info, stat, 1);
*update = 1;
}
@@ -397,9 +397,9 @@ out:
rcu_read_unlock();
}
void mt76_mac_poll_tx_status(struct mt76_dev *dev, bool irq)
void mt76x2_mac_poll_tx_status(struct mt76x2_dev *dev, bool irq)
{
struct mt76_tx_status stat = {};
struct mt76x2_tx_status stat = {};
unsigned long flags;
u8 update = 1;
@@ -412,13 +412,13 @@ void mt76_mac_poll_tx_status(struct mt76_dev *dev, bool irq)
u32 stat1, stat2;
spin_lock_irqsave(&dev->irq_lock, flags);
stat1 = mt76_rr(dev, MT_TX_STAT_FIFO);
stat1 = mt76x2_rr(dev, MT_TX_STAT_FIFO);
if (!(stat1 & MT_TX_STAT_FIFO_VALID)) {
spin_unlock_irqrestore(&dev->irq_lock, flags);
break;
}
stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT);
stat2 = mt76x2_rr(dev, MT_TX_STAT_FIFO_EXT);
spin_unlock_irqrestore(&dev->irq_lock, flags);
stat.valid = 1;
@@ -432,7 +432,7 @@ void mt76_mac_poll_tx_status(struct mt76_dev *dev, bool irq)
trace_mac_txstat_fetch(dev, &stat);
if (!irq) {
mt76_send_tx_status(dev, &stat, &update);
mt76x2_send_tx_status(dev, &stat, &update);
continue;
}
@@ -440,32 +440,32 @@ void mt76_mac_poll_tx_status(struct mt76_dev *dev, bool irq)
}
}
void mt76_mac_queue_txdone(struct mt76_dev *dev, struct sk_buff *skb,
struct mt76_txwi *txwi)
void mt76x2_mac_queue_txdone(struct mt76x2_dev *dev, struct sk_buff *skb,
struct mt76x2_txwi *txwi)
{
struct mt76_tx_info *txi = mt76_skb_tx_info(skb);
struct mt76x2_tx_info *txi = mt76x2_skb_tx_info(skb);
mt76_mac_poll_tx_status(dev, false);
mt76x2_mac_poll_tx_status(dev, false);
txi->tries = 0;
txi->jiffies = jiffies;
txi->wcid = txwi->wcid;
txi->pktid = txwi->pktid;
trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid);
mt76_tx_complete(dev, skb);
mt76x2_tx_complete(dev, skb);
}
void mt76_mac_process_tx_status_fifo(struct mt76_dev *dev)
void mt76x2_mac_process_tx_status_fifo(struct mt76x2_dev *dev)
{
struct mt76_tx_status stat;
struct mt76x2_tx_status stat;
u8 update = 1;
while (kfifo_get(&dev->txstatus_fifo, &stat))
mt76_send_tx_status(dev, &stat, &update);
mt76x2_send_tx_status(dev, &stat, &update);
}
static enum mt76_cipher_type
mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
static enum mt76x2_cipher_type
mt76x2_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
{
memset(key_data, 0, 32);
if (!key)
@@ -490,72 +490,72 @@ mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
}
}
void mt76_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
void mt76x2_mac_wcid_setup(struct mt76x2_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
{
struct mt76_wcid_addr addr = {};
struct mt76x2_wcid_addr addr = {};
u32 attr;
attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
mt76_wr(dev, MT_WCID_ATTR(idx), attr);
mt76x2_wr(dev, MT_WCID_ATTR(idx), attr);
if (mac)
memcpy(addr.macaddr, mac, ETH_ALEN);
mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
mt76x2_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
}
int mt76_mac_wcid_set_key(struct mt76_dev *dev, u8 idx,
int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx,
struct ieee80211_key_conf *key)
{
enum mt76_cipher_type cipher;
enum mt76x2_cipher_type cipher;
u8 key_data[32];
u8 iv_data[8];
cipher = mt76_mac_get_key_info(key, key_data);
cipher = mt76x2_mac_get_key_info(key, key_data);
if (cipher == MT_CIPHER_NONE && key)
return -EINVAL;
mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
mt76x2_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
mt76x2_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
memset(iv_data, 0, sizeof(iv_data));
if (key) {
mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
mt76x2_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
!!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
iv_data[3] = key->keyidx << 6;
if (cipher >= MT_CIPHER_TKIP)
iv_data[3] |= 0x20;
}
mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
mt76x2_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
return 0;
}
int mt76_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx,
int mt76x2_mac_shared_key_setup(struct mt76x2_dev *dev, u8 vif_idx, u8 key_idx,
struct ieee80211_key_conf *key)
{
enum mt76_cipher_type cipher;
enum mt76x2_cipher_type cipher;
u8 key_data[32];
u32 val;
cipher = mt76_mac_get_key_info(key, key_data);
cipher = mt76x2_mac_get_key_info(key, key_data);
if (cipher == MT_CIPHER_NONE && key)
return -EINVAL;
val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
val = mt76x2_rr(dev, MT_SKEY_MODE(vif_idx));
val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
mt76x2_wr(dev, MT_SKEY_MODE(vif_idx), val);
mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, sizeof(key_data));
mt76x2_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, sizeof(key_data));
return 0;
}
int mt76_mac_skb_tx_overhead(struct mt76_dev *dev, struct sk_buff *skb)
int mt76x2_mac_skb_tx_overhead(struct mt76x2_dev *dev, struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct ieee80211_key_conf *key = info->control.hw_key;
@@ -576,26 +576,26 @@ int mt76_mac_skb_tx_overhead(struct mt76_dev *dev, struct sk_buff *skb)
}
static int
mt76_write_beacon(struct mt76_dev *dev, int offset, struct sk_buff *skb)
mt76x2_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
{
int beacon_len = dev->beacon_offsets[1] - dev->beacon_offsets[0];
struct mt76_txwi txwi;
struct mt76x2_txwi txwi;
if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76_txwi)))
if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x2_txwi)))
return -ENOSPC;
mt76_mac_write_txwi(dev, &txwi, skb, NULL, NULL);
mt76x2_mac_write_txwi(dev, &txwi, skb, NULL, NULL);
txwi.flags |= cpu_to_le16(MT_TXWI_FLAGS_TS);
mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
mt76x2_wr_copy(dev, offset, &txwi, sizeof(txwi));
offset += sizeof(txwi);
mt76_wr_copy(dev, offset, skb->data, skb->len);
mt76x2_wr_copy(dev, offset, skb->data, skb->len);
return 0;
}
static int
__mt76_mac_set_beacon(struct mt76_dev *dev, u8 bcn_idx, struct sk_buff *skb)
__mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 bcn_idx, struct sk_buff *skb)
{
int beacon_len = dev->beacon_offsets[1] - dev->beacon_offsets[0];
int beacon_addr = dev->beacon_offsets[bcn_idx];
@@ -603,24 +603,24 @@ __mt76_mac_set_beacon(struct mt76_dev *dev, u8 bcn_idx, struct sk_buff *skb)
int i;
/* Prevent corrupt transmissions during update */
mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
mt76x2_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
if (skb) {
ret = mt76_write_beacon(dev, beacon_addr, skb);
ret = mt76x2_write_beacon(dev, beacon_addr, skb);
if (!ret)
dev->beacon_data_mask |= BIT(bcn_idx) & dev->beacon_mask;
} else {
dev->beacon_data_mask &= ~BIT(bcn_idx);
for (i = 0; i < beacon_len; i += 4)
mt76_wr(dev, beacon_addr + i, 0);
mt76x2_wr(dev, beacon_addr + i, 0);
}
mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask);
mt76x2_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask);
return ret;
}
int mt76_mac_set_beacon(struct mt76_dev *dev, u8 vif_idx, struct sk_buff *skb)
int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx, struct sk_buff *skb)
{
bool force_update = false;
int bcn_idx = 0;
@@ -634,9 +634,9 @@ int mt76_mac_set_beacon(struct mt76_dev *dev, u8 vif_idx, struct sk_buff *skb)
dev_kfree_skb(dev->beacons[i]);
dev->beacons[i] = skb;
__mt76_mac_set_beacon(dev, bcn_idx, skb);
__mt76x2_mac_set_beacon(dev, bcn_idx, skb);
} else if (force_update && dev->beacons[i]) {
__mt76_mac_set_beacon(dev, bcn_idx, dev->beacons[i]);
__mt76x2_mac_set_beacon(dev, bcn_idx, dev->beacons[i]);
}
bcn_idx += !!dev->beacons[i];
@@ -646,14 +646,14 @@ int mt76_mac_set_beacon(struct mt76_dev *dev, u8 vif_idx, struct sk_buff *skb)
if (!(dev->beacon_data_mask & BIT(i)))
break;
__mt76_mac_set_beacon(dev, i, NULL);
__mt76x2_mac_set_beacon(dev, i, NULL);
}
mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, bcn_idx - 1);
mt76x2_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, bcn_idx - 1);
return 0;
}
void mt76_mac_set_beacon_enable(struct mt76_dev *dev, u8 vif_idx, bool val)
void mt76x2_mac_set_beacon_enable(struct mt76x2_dev *dev, u8 vif_idx, bool val)
{
u8 old_mask = dev->beacon_mask;
bool en;
@@ -663,7 +663,7 @@ void mt76_mac_set_beacon_enable(struct mt76_dev *dev, u8 vif_idx, bool val)
dev->beacon_mask |= BIT(vif_idx);
} else {
dev->beacon_mask &= ~BIT(vif_idx);
mt76_mac_set_beacon(dev, vif_idx, NULL);
mt76x2_mac_set_beacon(dev, vif_idx, NULL);
}
if (!!old_mask == !!dev->beacon_mask)
@@ -671,26 +671,26 @@ void mt76_mac_set_beacon_enable(struct mt76_dev *dev, u8 vif_idx, bool val)
en = dev->beacon_mask;
mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
mt76x2_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
reg = MT_BEACON_TIME_CFG_BEACON_TX |
MT_BEACON_TIME_CFG_TBTT_EN |
MT_BEACON_TIME_CFG_TIMER_EN;
mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
mt76x2_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
if (en)
mt76_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
mt76x2_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
else
mt76_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
mt76x2_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
}
void mt76_mac_work(struct work_struct *work)
void mt76x2_mac_work(struct work_struct *work)
{
struct mt76_dev *dev = container_of(work, struct mt76_dev,
struct mt76x2_dev *dev = container_of(work, struct mt76x2_dev,
mac_work.work);
int i, idx;
for (i = 0, idx = 0; i < 16; i++) {
u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
u32 val = mt76x2_rr(dev, MT_TX_AGG_CNT(i));
dev->aggr_stats[idx++] += val & 0xffff;
dev->aggr_stats[idx++] += val >> 16;
}
mac.h
+37 -37
View File
@@ -14,16 +14,16 @@
#ifndef __MT76_MAC_H
#define __MT76_MAC_H
struct mt76_dev;
struct mt76_sta;
struct mt76_vif;
struct mt76_wcid;
struct mt76x2_dev;
struct mt76x2_sta;
struct mt76x2_vif;
struct mt76x2_wcid;
struct mt76_txwi;
struct mt76_queue;
struct mt76_txwi_cache;
struct mt76x2_txwi;
struct mt76x2_queue;
struct mt76x2_txwi_cache;
struct mt76_tx_status {
struct mt76x2_tx_status {
u8 valid:1;
u8 success:1;
u8 aggr:1;
@@ -34,7 +34,7 @@ struct mt76_tx_status {
u16 rate;
} __packed __aligned(2);
struct mt76_tx_info {
struct mt76x2_tx_info {
unsigned long jiffies;
u8 tries;
@@ -43,7 +43,7 @@ struct mt76_tx_info {
u8 retry;
};
struct mt76_rxwi {
struct mt76x2_rxwi {
__le32 rxinfo;
__le32 ctl;
@@ -107,7 +107,7 @@ struct mt76_rxwi {
#define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
#define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
enum mt76_phy_type {
enum mt76x2_phy_type {
MT_PHY_TYPE_CCK,
MT_PHY_TYPE_OFDM,
MT_PHY_TYPE_HT,
@@ -115,7 +115,7 @@ enum mt76_phy_type {
MT_PHY_TYPE_VHT,
};
enum mt76_phy_bandwith {
enum mt76x2_phy_bandwith {
MT_PHY_BW_20,
MT_PHY_BW_40,
MT_PHY_BW_80,
@@ -140,7 +140,7 @@ enum mt76_phy_bandwith {
#define MT_TXWI_PKTID_PROBE BIT(7)
struct mt76_txwi {
struct mt76x2_txwi {
__le16 flags;
__le16 rate;
u8 ack_ctl;
@@ -155,45 +155,45 @@ struct mt76_txwi {
} __packed __aligned(4);
static inline struct mt76_tx_info *
mt76_skb_tx_info(struct sk_buff *skb)
static inline struct mt76x2_tx_info *
mt76x2_skb_tx_info(struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
return (void *) info->status.status_driver_data;
}
int mt76_mac_reset(struct mt76_dev *dev, bool hard);
int mt76_mac_start(struct mt76_dev *dev);
void mt76_mac_stop(struct mt76_dev *dev, bool force);
void mt76_mac_resume(struct mt76_dev *dev);
void mt76_mac_set_bssid(struct mt76_dev *dev, u8 idx, const u8 *addr);
int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard);
int mt76x2_mac_start(struct mt76x2_dev *dev);
void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force);
void mt76x2_mac_resume(struct mt76x2_dev *dev);
void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr);
int mt76_mac_process_rx(struct mt76_dev *dev, struct sk_buff *skb, void *rxwi);
void mt76_mac_write_txwi(struct mt76_dev *dev, struct mt76_txwi *txwi,
struct sk_buff *skb, struct mt76_wcid *wcid,
int mt76x2_mac_process_rx(struct mt76x2_dev *dev, struct sk_buff *skb, void *rxwi);
void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
struct sk_buff *skb, struct mt76x2_wcid *wcid,
struct ieee80211_sta *sta);
void mt76_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
int mt76_mac_wcid_set_key(struct mt76_dev *dev, u8 idx,
void mt76x2_mac_wcid_setup(struct mt76x2_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx,
struct ieee80211_key_conf *key);
void mt76_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid,
void mt76x2_mac_wcid_set_rate(struct mt76x2_dev *dev, struct mt76x2_wcid *wcid,
const struct ieee80211_tx_rate *rate);
int mt76_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx,
int mt76x2_mac_shared_key_setup(struct mt76x2_dev *dev, u8 vif_idx, u8 key_idx,
struct ieee80211_key_conf *key);
int mt76_insert_hdr_pad(struct sk_buff *skb);
void mt76_remove_hdr_pad(struct sk_buff *skb);
int mt76_mac_skb_tx_overhead(struct mt76_dev *dev, struct sk_buff *skb);
int mt76x2_insert_hdr_pad(struct sk_buff *skb);
void mt76x2_remove_hdr_pad(struct sk_buff *skb);
int mt76x2_mac_skb_tx_overhead(struct mt76x2_dev *dev, struct sk_buff *skb);
int mt76_mac_set_beacon(struct mt76_dev *dev, u8 vif_idx, struct sk_buff *skb);
void mt76_mac_set_beacon_enable(struct mt76_dev *dev, u8 vif_idx, bool val);
int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx, struct sk_buff *skb);
void mt76x2_mac_set_beacon_enable(struct mt76x2_dev *dev, u8 vif_idx, bool val);
void mt76_mac_queue_txdone(struct mt76_dev *dev, struct sk_buff *skb,
struct mt76_txwi *txwi);
void mt76x2_mac_queue_txdone(struct mt76x2_dev *dev, struct sk_buff *skb,
struct mt76x2_txwi *txwi);
void mt76_mac_poll_tx_status(struct mt76_dev *dev, bool irq);
void mt76_mac_process_tx_status_fifo(struct mt76_dev *dev);
void mt76x2_mac_poll_tx_status(struct mt76x2_dev *dev, bool irq);
void mt76x2_mac_process_tx_status_fifo(struct mt76x2_dev *dev);
void mt76_mac_work(struct work_struct *work);
void mt76x2_mac_work(struct work_struct *work);
#endif
main.c
+112 -112
View File
@@ -14,18 +14,18 @@
#include "mt76.h"
static int
mt76_start(struct ieee80211_hw *hw)
mt76x2_start(struct ieee80211_hw *hw)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
int ret;
mutex_lock(&dev->mutex);
ret = mt76_mac_start(dev);
ret = mt76x2_mac_start(dev);
if (ret)
goto out;
ret = mt76_phy_start(dev);
ret = mt76x2_phy_start(dev);
if (ret)
goto out;
@@ -41,22 +41,22 @@ out:
}
static void
mt76_stop(struct ieee80211_hw *hw)
mt76x2_stop(struct ieee80211_hw *hw)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
mutex_lock(&dev->mutex);
napi_disable(&dev->napi);
clear_bit(MT76_STATE_RUNNING, &dev->state);
mt76_stop_hardware(dev);
mt76x2_stop_hardware(dev);
mutex_unlock(&dev->mutex);
}
static int
mt76_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
mt76x2_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
{
struct mt76_dev *dev = hw->priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
unsigned int idx = 0;
int ret = 0;
@@ -82,23 +82,23 @@ mt76_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
mvif->idx = idx;
mvif->group_wcid.idx = 254 - idx;
mvif->group_wcid.hw_key_idx = -1;
mt76_txq_init(dev, vif->txq);
mt76x2_txq_init(dev, vif->txq);
return ret;
}
static void
mt76_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
mt76x2_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
mt76_txq_remove(dev, vif->txq);
mt76x2_txq_remove(dev, vif->txq);
}
static int
mt76_config(struct ieee80211_hw *hw, u32 changed)
mt76x2_config(struct ieee80211_hw *hw, u32 changed)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
int ret = 0;
mutex_lock(&dev->mutex);
@@ -107,12 +107,12 @@ mt76_config(struct ieee80211_hw *hw, u32 changed)
dev->txpower_conf = hw->conf.power_level * 2;
if (test_bit(MT76_STATE_RUNNING, &dev->state))
mt76_phy_set_txpower(dev);
mt76x2_phy_set_txpower(dev);
}
if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
ieee80211_stop_queues(hw);
ret = mt76_set_channel(dev, &hw->conf.chandef);
ret = mt76x2_set_channel(dev, &hw->conf.chandef);
ieee80211_wake_queues(hw);
}
@@ -122,10 +122,10 @@ mt76_config(struct ieee80211_hw *hw, u32 changed)
}
static void
mt76_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
mt76x2_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
unsigned int *total_flags, u64 multicast)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
u32 flags = 0;
#define MT76_FILTER(_flag, _hw) do { \
@@ -149,31 +149,31 @@ mt76_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL);
*total_flags = flags;
mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
mt76x2_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
mutex_unlock(&dev->mutex);
}
static void
mt76_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_bss_conf *info, u32 changed)
{
struct mt76_dev *dev = hw->priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
mutex_lock(&dev->mutex);
if (changed & BSS_CHANGED_BSSID)
mt76_mac_set_bssid(dev, mvif->idx, info->bssid);
mt76x2_mac_set_bssid(dev, mvif->idx, info->bssid);
if (changed & BSS_CHANGED_BEACON_INT)
mt76_rmw_field(dev, MT_BEACON_TIME_CFG,
mt76x2_rmw_field(dev, MT_BEACON_TIME_CFG,
MT_BEACON_TIME_CFG_INTVAL,
info->beacon_int << 4);
if (changed & BSS_CHANGED_BEACON_ENABLED) {
tasklet_disable(&dev->pre_tbtt_tasklet);
mt76_mac_set_beacon_enable(dev, mvif->idx, info->enable_beacon);
mt76x2_mac_set_beacon_enable(dev, mvif->idx, info->enable_beacon);
tasklet_enable(&dev->pre_tbtt_tasklet);
}
@@ -181,7 +181,7 @@ mt76_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
int slottime = info->use_short_slot ? 9 : 20;
dev->slottime = slottime;
mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
mt76x2_rmw_field(dev, MT_BKOFF_SLOT_CFG,
MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
}
@@ -189,7 +189,7 @@ mt76_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
}
static int
mt76_wcid_alloc(struct mt76_dev *dev)
mt76x2_wcid_alloc(struct mt76x2_dev *dev)
{
int i, idx = 0;
@@ -211,19 +211,19 @@ mt76_wcid_alloc(struct mt76_dev *dev)
}
static int
mt76_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
int ret = 0;
int idx = 0;
int i;
mutex_lock(&dev->mutex);
idx = mt76_wcid_alloc(dev);
idx = mt76x2_wcid_alloc(dev);
if (idx < 0) {
ret = -ENOSPC;
goto out;
@@ -231,10 +231,10 @@ mt76_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
msta->wcid.idx = idx;
msta->wcid.hw_key_idx = -1;
mt76_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76x2_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
mt76x2_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76_txq_init(dev, sta->txq[i]);
mt76x2_txq_init(dev, sta->txq[i]);
rcu_assign_pointer(dev->wcid[idx], &msta->wcid);
@@ -245,56 +245,56 @@ out:
}
static int
mt76_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
int idx = msta->wcid.idx;
int i;
mutex_lock(&dev->mutex);
rcu_assign_pointer(dev->wcid[idx], NULL);
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
mt76_txq_remove(dev, sta->txq[i]);
mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76x2_txq_remove(dev, sta->txq[i]);
mt76x2_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG);
mt76_mac_wcid_setup(dev, idx, 0, NULL);
mt76x2_mac_wcid_setup(dev, idx, 0, NULL);
mutex_unlock(&dev->mutex);
return 0;
}
static void
mt76_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
{
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76_dev *dev = hw->priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
struct mt76x2_dev *dev = hw->priv;
int idx = msta->wcid.idx;
switch (cmd) {
case STA_NOTIFY_SLEEP:
msta->sleeping = true;
mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76_stop_tx_queues(dev, sta);
mt76x2_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76x2_stop_tx_queues(dev, sta);
break;
case STA_NOTIFY_AWAKE:
mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
mt76x2_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx));
msta->sleeping = false;
break;
}
}
static int
mt76_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
mt76x2_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
struct ieee80211_vif *vif, struct ieee80211_sta *sta,
struct ieee80211_key_conf *key)
{
struct mt76_dev *dev = hw->priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76_sta *msta = sta ? (struct mt76_sta *) sta->drv_priv : NULL;
struct mt76_wcid *wcid = msta ? &msta->wcid : &mvif->group_wcid;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
struct mt76x2_sta *msta = sta ? (struct mt76x2_sta *) sta->drv_priv : NULL;
struct mt76x2_wcid *wcid = msta ? &msta->wcid : &mvif->group_wcid;
int idx = key->keyidx;
int ret;
@@ -310,22 +310,22 @@ mt76_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
if (!msta) {
if (key || wcid->hw_key_idx == idx) {
ret = mt76_mac_wcid_set_key(dev, wcid->idx, key);
ret = mt76x2_mac_wcid_set_key(dev, wcid->idx, key);
if (ret)
return ret;
}
return mt76_mac_shared_key_setup(dev, mvif->idx, idx, key);
return mt76x2_mac_shared_key_setup(dev, mvif->idx, idx, key);
}
return mt76_mac_wcid_set_key(dev, msta->wcid.idx, key);
return mt76x2_mac_wcid_set_key(dev, msta->wcid.idx, key);
}
static int
mt76_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
const struct ieee80211_tx_queue_params *params)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
u8 cw_min = 5, cw_max = 10;
u32 val;
@@ -338,84 +338,84 @@ mt76_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) |
MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) |
MT76_SET(MT_EDCA_CFG_CWMAX, cw_max);
mt76_wr(dev, MT_EDCA_CFG_AC(queue), val);
mt76x2_wr(dev, MT_EDCA_CFG_AC(queue), val);
val = mt76_rr(dev, MT_WMM_TXOP(queue));
val = mt76x2_rr(dev, MT_WMM_TXOP(queue));
val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue));
val |= params->txop << MT_WMM_TXOP_SHIFT(queue);
mt76_wr(dev, MT_WMM_TXOP(queue), val);
mt76x2_wr(dev, MT_WMM_TXOP(queue), val);
val = mt76_rr(dev, MT_WMM_AIFSN);
val = mt76x2_rr(dev, MT_WMM_AIFSN);
val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue));
val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue);
mt76_wr(dev, MT_WMM_AIFSN, val);
mt76x2_wr(dev, MT_WMM_AIFSN, val);
val = mt76_rr(dev, MT_WMM_CWMIN);
val = mt76x2_rr(dev, MT_WMM_CWMIN);
val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue));
val |= cw_min << MT_WMM_CWMIN_SHIFT(queue);
mt76_wr(dev, MT_WMM_CWMIN, val);
mt76x2_wr(dev, MT_WMM_CWMIN, val);
val = mt76_rr(dev, MT_WMM_CWMAX);
val = mt76x2_rr(dev, MT_WMM_CWMAX);
val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue));
val |= cw_max << MT_WMM_CWMAX_SHIFT(queue);
mt76_wr(dev, MT_WMM_CWMAX, val);
mt76x2_wr(dev, MT_WMM_CWMAX, val);
return 0;
}
static void
mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const u8 *mac)
mt76x2_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, const u8 *mac)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
tasklet_disable(&dev->pre_tbtt_tasklet);
set_bit(MT76_SCANNING, &dev->state);
}
static void
mt76_sw_scan_complete(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
mt76x2_sw_scan_complete(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
clear_bit(MT76_SCANNING, &dev->state);
tasklet_enable(&dev->pre_tbtt_tasklet);
}
static void
mt76_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
u32 queues, bool drop)
{
}
static int
mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, int *dbm)
mt76x2_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, int *dbm)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
*dbm = dev->txpower_cur / 2;
return 0;
}
static int
mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
enum ieee80211_ampdu_mlme_action action,
struct ieee80211_sta *sta,u16 tid, u16 *ssn, u8 buf_size,
bool amsdu)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
struct ieee80211_txq *txq = sta->txq[tid];
struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
struct mt76x2_txq *mtxq = (struct mt76x2_txq *) txq->drv_priv;
if (!txq)
return -EINVAL;
switch (action) {
case IEEE80211_AMPDU_RX_START:
mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
mt76x2_set(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
break;
case IEEE80211_AMPDU_RX_STOP:
mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
mt76x2_clear(dev, MT_WCID_ADDR(msta->wcid.idx)+4, BIT(16 + tid));
break;
case IEEE80211_AMPDU_TX_OPERATIONAL:
mtxq->aggr = true;
@@ -440,11 +440,11 @@ mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
}
static void
mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
mt76x2_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
struct mt76_dev *dev = hw->priv;
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates);
struct ieee80211_tx_rate rate = {};
@@ -453,46 +453,46 @@ mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
rate.idx = rates->rate[0].idx;
rate.flags = rates->rate[0].flags;
mt76_mac_wcid_set_rate(dev, &msta->wcid, &rate);
mt76x2_mac_wcid_set_rate(dev, &msta->wcid, &rate);
}
static void mt76_set_coverage_class(struct ieee80211_hw *hw,
static void mt76x2_set_coverage_class(struct ieee80211_hw *hw,
s16 coverage_class)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
mutex_lock(&dev->mutex);
dev->coverage_class = coverage_class;
mt76_set_tx_ackto(dev);
mt76x2_set_tx_ackto(dev);
mutex_unlock(&dev->mutex);
}
const struct ieee80211_ops mt76_ops = {
.tx = mt76_tx,
.start = mt76_start,
.stop = mt76_stop,
.add_interface = mt76_add_interface,
.remove_interface = mt76_remove_interface,
.config = mt76_config,
.configure_filter = mt76_configure_filter,
.bss_info_changed = mt76_bss_info_changed,
.sta_add = mt76_sta_add,
.sta_remove = mt76_sta_remove,
.sta_notify = mt76_sta_notify,
.set_key = mt76_set_key,
.conf_tx = mt76_conf_tx,
.sw_scan_start = mt76_sw_scan,
.sw_scan_complete = mt76_sw_scan_complete,
.flush = mt76_flush,
.ampdu_action = mt76_ampdu_action,
.get_txpower = mt76_get_txpower,
.wake_tx_queue = mt76_wake_tx_queue,
.sta_rate_tbl_update = mt76_sta_rate_tbl_update,
.release_buffered_frames = mt76_release_buffered_frames,
.set_coverage_class = mt76_set_coverage_class,
const struct ieee80211_ops mt76x2_ops = {
.tx = mt76x2_tx,
.start = mt76x2_start,
.stop = mt76x2_stop,
.add_interface = mt76x2_add_interface,
.remove_interface = mt76x2_remove_interface,
.config = mt76x2_config,
.configure_filter = mt76x2_configure_filter,
.bss_info_changed = mt76x2_bss_info_changed,
.sta_add = mt76x2_sta_add,
.sta_remove = mt76x2_sta_remove,
.sta_notify = mt76x2_sta_notify,
.set_key = mt76x2_set_key,
.conf_tx = mt76x2_conf_tx,
.sw_scan_start = mt76x2_sw_scan,
.sw_scan_complete = mt76x2_sw_scan_complete,
.flush = mt76x2_flush,
.ampdu_action = mt76x2_ampdu_action,
.get_txpower = mt76x2_get_txpower,
.wake_tx_queue = mt76x2_wake_tx_queue,
.sta_rate_tbl_update = mt76x2_sta_rate_tbl_update,
.release_buffered_frames = mt76x2_release_buffered_frames,
.set_coverage_class = mt76x2_set_coverage_class,
};
void mt76_rx(struct mt76_dev *dev, struct sk_buff *skb)
void mt76x2_rx(struct mt76x2_dev *dev, struct sk_buff *skb)
{
if (!test_bit(MT76_STATE_RUNNING, &dev->state)) {
dev_kfree_skb(skb);
mcu.c
+60 -60
View File
@@ -20,7 +20,7 @@
#include "dma.h"
#include "eeprom.h"
struct mt76_fw_header {
struct mt76x2_fw_header {
__le32 ilm_len;
__le32 dlm_len;
__le16 build_ver;
@@ -29,7 +29,7 @@ struct mt76_fw_header {
char build_time[16];
};
struct mt76_patch_header {
struct mt76x2_patch_header {
char build_time[16];
char platform[4];
char hw_version[4];
@@ -38,7 +38,7 @@ struct mt76_patch_header {
};
static struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, int len)
mt76x2_mcu_msg_alloc(struct mt76x2_dev *dev, const void *data, int len)
{
struct sk_buff *skb;
@@ -49,7 +49,7 @@ mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, int len)
}
static struct sk_buff *
mt76_mcu_get_response(struct mt76_dev *dev, unsigned long expires)
mt76x2_mcu_get_response(struct mt76x2_dev *dev, unsigned long expires)
{
unsigned long timeout;
@@ -63,7 +63,7 @@ mt76_mcu_get_response(struct mt76_dev *dev, unsigned long expires)
}
static int
mt76_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb, enum mcu_cmd cmd)
mt76x2_mcu_msg_send(struct mt76x2_dev *dev, struct sk_buff *skb, enum mcu_cmd cmd)
{
unsigned long expires = jiffies + HZ;
int ret;
@@ -78,7 +78,7 @@ mt76_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb, enum mcu_cmd cmd)
if (!seq)
seq = ++dev->mcu.msg_seq & 0xf;
ret = mt76_tx_queue_mcu(dev, MT_TXQ_MCU, skb, cmd, seq);
ret = mt76x2_tx_queue_mcu(dev, MT_TXQ_MCU, skb, cmd, seq);
if (ret)
goto out;
@@ -86,7 +86,7 @@ mt76_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb, enum mcu_cmd cmd)
u32 *rxfce;
bool check_seq = false;
skb = mt76_mcu_get_response(dev, expires);
skb = mt76x2_mcu_get_response(dev, expires);
if (!skb) {
printk("MCU message %d (seq %d) timed out\n", cmd, seq);
ret = -ETIMEDOUT;
@@ -110,22 +110,22 @@ out:
}
static void
write_data(struct mt76_dev *dev, u32 offset, __le32 *data, int len)
write_data(struct mt76x2_dev *dev, u32 offset, __le32 *data, int len)
{
__iowrite32_copy(dev->regs + offset, data, len / 4);
}
static int
mt76pci_load_rom_patch(struct mt76_dev *dev)
mt76pci_load_rom_patch(struct mt76x2_dev *dev)
{
const struct firmware *fw = NULL;
struct mt76_patch_header *hdr;
struct mt76x2_patch_header *hdr;
bool rom_protect = !is_mt7612(dev);
int len, ret = 0;
__le32 *cur;
u32 patch_mask, patch_reg;
if (rom_protect && !mt76_poll(dev, MT_MCU_SEMAPHORE_03, 1, 1, 600)) {
if (rom_protect && !mt76x2_poll(dev, MT_MCU_SEMAPHORE_03, 1, 1, 600)) {
printk("Could not get hardware semaphore for ROM PATCH\n");
return -ETIMEDOUT;
}
@@ -138,7 +138,7 @@ mt76pci_load_rom_patch(struct mt76_dev *dev)
patch_reg = MT_MCU_COM_REG0;
}
if (rom_protect && (mt76_rr(dev, patch_reg) & patch_mask)) {
if (rom_protect && (mt76x2_rr(dev, patch_reg) & patch_mask)) {
printk("ROM patch already applied\n");
goto out;
}
@@ -153,21 +153,21 @@ mt76pci_load_rom_patch(struct mt76_dev *dev)
goto out;
}
hdr = (struct mt76_patch_header *) fw->data;
hdr = (struct mt76x2_patch_header *) fw->data;
printk("ROM patch build: %.15s\n", hdr->build_time);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ROM_PATCH_OFFSET);
mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ROM_PATCH_OFFSET);
cur = (__le32 *) (fw->data + sizeof(*hdr));
len = fw->size - sizeof(*hdr);
write_data(dev, MT_MCU_ROM_PATCH_ADDR, cur, len);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
/* Trigger ROM */
mt76_wr(dev, MT_MCU_INT_LEVEL, 4);
mt76x2_wr(dev, MT_MCU_INT_LEVEL, 4);
if (!mt76_poll_msec(dev, patch_reg, patch_mask, patch_mask, 2000)) {
if (!mt76x2_poll_msec(dev, patch_reg, patch_mask, patch_mask, 2000)) {
printk("Failed to load ROM patch\n");
ret = -ETIMEDOUT;
}
@@ -175,16 +175,16 @@ mt76pci_load_rom_patch(struct mt76_dev *dev)
out:
/* release semaphore */
if (rom_protect)
mt76_wr(dev, MT_MCU_SEMAPHORE_03, 1);
mt76x2_wr(dev, MT_MCU_SEMAPHORE_03, 1);
release_firmware(fw);
return ret;
}
static int
mt76pci_load_firmware(struct mt76_dev *dev)
mt76pci_load_firmware(struct mt76x2_dev *dev)
{
const struct firmware *fw;
const struct mt76_fw_header *hdr;
const struct mt76x2_fw_header *hdr;
int i, len, ret;
__le32 *cur;
u32 offset, val;
@@ -196,7 +196,7 @@ mt76pci_load_firmware(struct mt76_dev *dev)
if (!fw || !fw->data || fw->size < sizeof(*hdr))
goto error;
hdr = (const struct mt76_fw_header *) fw->data;
hdr = (const struct mt76x2_fw_header *) fw->data;
len = sizeof(*hdr);
len += le32_to_cpu(hdr->ilm_len);
@@ -216,7 +216,7 @@ mt76pci_load_firmware(struct mt76_dev *dev)
cur = (__le32 *) (fw->data + sizeof(*hdr));
len = le32_to_cpu(hdr->ilm_len);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ILM_OFFSET);
mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ILM_OFFSET);
write_data(dev, MT_MCU_ILM_ADDR, cur, len);
cur += len / sizeof(*cur);
@@ -227,19 +227,19 @@ mt76pci_load_firmware(struct mt76_dev *dev)
else
offset = MT_MCU_DLM_ADDR;
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_DLM_OFFSET);
mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_DLM_OFFSET);
write_data(dev, offset, cur, len);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
mt76x2_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_2);
val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
if (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
mt76_set(dev, MT_MCU_COM_REG0, BIT(30));
mt76x2_set(dev, MT_MCU_COM_REG0, BIT(30));
/* trigger firmware */
mt76_wr(dev, MT_MCU_INT_LEVEL, 2);
mt76x2_wr(dev, MT_MCU_INT_LEVEL, 2);
for (i = 200; i > 0; i--) {
val = mt76_rr(dev, MT_MCU_COM_REG0);
val = mt76x2_rr(dev, MT_MCU_COM_REG0);
if (val & 1)
break;
@@ -266,7 +266,7 @@ error:
}
static int
mt76_mcu_function_select(struct mt76_dev *dev, enum mcu_function func, u32 val)
mt76x2_mcu_function_select(struct mt76x2_dev *dev, enum mcu_function func, u32 val)
{
struct sk_buff *skb;
struct {
@@ -277,11 +277,11 @@ mt76_mcu_function_select(struct mt76_dev *dev, enum mcu_function func, u32 val)
.value = cpu_to_le32(val),
};
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_FUN_SET_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_FUN_SET_OP);
}
int mt76_mcu_load_cr(struct mt76_dev *dev, u8 type, u8 temp_level, u8 channel)
int mt76x2_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level, u8 channel)
{
struct sk_buff *skb;
struct {
@@ -299,16 +299,16 @@ int mt76_mcu_load_cr(struct mt76_dev *dev, u8 type, u8 temp_level, u8 channel)
u32 val;
val = BIT(31);
val |= (mt76_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff;
val |= (mt76_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00;
val |= (mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff;
val |= (mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00;
msg.cfg = cpu_to_le32(val);
/* first set the channel without the extension channel info */
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_LOAD_CR);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_LOAD_CR);
}
int mt76_mcu_set_channel(struct mt76_dev *dev, u8 channel, u8 bw, u8 bw_index,
int mt76x2_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw, u8 bw_index,
bool scan)
{
struct sk_buff *skb;
@@ -330,17 +330,17 @@ int mt76_mcu_set_channel(struct mt76_dev *dev, u8 channel, u8 bw, u8 bw_index,
};
/* first set the channel without the extension channel info */
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
mt76_mcu_msg_send(dev, skb, CMD_SWITCH_CHANNEL_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
mt76x2_mcu_msg_send(dev, skb, CMD_SWITCH_CHANNEL_OP);
msleep(5);
msg.ext_chan = 0xe0 + bw_index;
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_SWITCH_CHANNEL_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_SWITCH_CHANNEL_OP);
}
int mt76_mcu_set_radio_state(struct mt76_dev *dev, bool on)
int mt76x2_mcu_set_radio_state(struct mt76x2_dev *dev, bool on)
{
struct sk_buff *skb;
struct {
@@ -351,11 +351,11 @@ int mt76_mcu_set_radio_state(struct mt76_dev *dev, bool on)
.level = cpu_to_le32(0),
};
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_POWER_SAVING_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_POWER_SAVING_OP);
}
int mt76_mcu_calibrate(struct mt76_dev *dev, enum mcu_calibration type,
int mt76x2_mcu_calibrate(struct mt76x2_dev *dev, enum mcu_calibration type,
u32 param)
{
struct sk_buff *skb;
@@ -368,36 +368,36 @@ int mt76_mcu_calibrate(struct mt76_dev *dev, enum mcu_calibration type,
};
int ret;
mt76_clear(dev, MT_MCU_COM_REG0, BIT(31));
mt76x2_clear(dev, MT_MCU_COM_REG0, BIT(31));
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
ret = mt76_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
ret = mt76x2_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP);
if (ret)
return ret;
if (WARN_ON(!mt76_poll_msec(dev, MT_MCU_COM_REG0,
if (WARN_ON(!mt76x2_poll_msec(dev, MT_MCU_COM_REG0,
BIT(31), BIT(31), 100)))
return -ETIMEDOUT;
return 0;
}
int mt76_mcu_tssi_comp(struct mt76_dev *dev, struct mt76_tssi_comp *tssi_data)
int mt76x2_mcu_tssi_comp(struct mt76x2_dev *dev, struct mt76x2_tssi_comp *tssi_data)
{
struct sk_buff *skb;
struct {
__le32 id;
struct mt76_tssi_comp data;
struct mt76x2_tssi_comp data;
} __packed __aligned(4) msg = {
.id = cpu_to_le32(MCU_CAL_TSSI_COMP),
.data = *tssi_data,
};
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP);
}
int mt76_mcu_init_gain(struct mt76_dev *dev, u8 channel, u32 gain, bool force)
int mt76x2_mcu_init_gain(struct mt76x2_dev *dev, u8 channel, u32 gain, bool force)
{
struct sk_buff *skb;
struct {
@@ -411,11 +411,11 @@ int mt76_mcu_init_gain(struct mt76_dev *dev, u8 channel, u32 gain, bool force)
if (force)
msg.channel |= cpu_to_le32(BIT(31));
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_INIT_GAIN_OP);
skb = mt76x2_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76x2_mcu_msg_send(dev, skb, CMD_INIT_GAIN_OP);
}
int mt76_mcu_init(struct mt76_dev *dev)
int mt76x2_mcu_init(struct mt76x2_dev *dev)
{
int ret;
@@ -429,13 +429,13 @@ int mt76_mcu_init(struct mt76_dev *dev)
if (ret)
return ret;
mt76_mcu_function_select(dev, Q_SELECT, 1);
mt76x2_mcu_function_select(dev, Q_SELECT, 1);
return 0;
}
int mt76_mcu_cleanup(struct mt76_dev *dev)
int mt76x2_mcu_cleanup(struct mt76x2_dev *dev)
{
mt76_wr(dev, MT_MCU_INT_LEVEL, 1);
mt76x2_wr(dev, MT_MCU_INT_LEVEL, 1);
msleep(20);
return 0;
mcu.h
+5 -5
View File
@@ -106,14 +106,14 @@ enum mcu_calibration {
MCU_CAL_TX_SHAPING,
};
enum mt76_mcu_cr_mode {
enum mt76x2_mcu_cr_mode {
MT_RF_CR,
MT_BBP_CR,
MT_RF_BBP_CR,
MT_HL_TEMP_CR_UPDATE,
};
struct mt76_tssi_comp {
struct mt76x2_tssi_comp {
u8 pa_mode;
u8 cal_mode;
u16 pad;
@@ -124,9 +124,9 @@ struct mt76_tssi_comp {
u8 offset1;
} __packed __aligned(4);
int mt76_mcu_calibrate(struct mt76_dev *dev, enum mcu_calibration type,
int mt76x2_mcu_calibrate(struct mt76x2_dev *dev, enum mcu_calibration type,
u32 param);
int mt76_mcu_tssi_comp(struct mt76_dev *dev, struct mt76_tssi_comp *data);
int mt76_mcu_init_gain(struct mt76_dev *dev, u8 channel, u32 gain, bool force);
int mt76x2_mcu_tssi_comp(struct mt76x2_dev *dev, struct mt76x2_tssi_comp *data);
int mt76x2_mcu_init_gain(struct mt76x2_dev *dev, u8 channel, u32 gain, bool force);
#endif
mt76.h
+101 -101
View File
@@ -48,11 +48,11 @@
#include "util.h"
#include "mac.h"
struct mt76_queue_entry {
struct mt76x2_queue_entry {
struct sk_buff *skb;
union {
void *buf;
struct mt76_txwi_cache *txwi;
struct mt76x2_txwi_cache *txwi;
};
bool schedule;
};
@@ -63,7 +63,7 @@ enum {
MT76_SCANNING,
};
enum mt76_txq_id {
enum mt76x2_txq_id {
MT_TXQ_VO = IEEE80211_AC_VO,
MT_TXQ_VI = IEEE80211_AC_VI,
MT_TXQ_BE = IEEE80211_AC_BE,
@@ -73,12 +73,12 @@ enum mt76_txq_id {
__MT_TXQ_MAX
};
struct mt76_queue {
struct mt76_queue_regs __iomem *regs;
struct mt76x2_queue {
struct mt76x2_queue_regs __iomem *regs;
spinlock_t lock;
struct mt76_queue_entry *entry;
struct mt76_desc *desc;
struct mt76x2_queue_entry *entry;
struct mt76x2_desc *desc;
struct list_head swq;
int swq_queued;
@@ -92,25 +92,25 @@ struct mt76_queue {
dma_addr_t desc_dma;
};
struct mt76_mcu {
struct mt76x2_mcu {
struct mutex mutex;
wait_queue_head_t wait;
struct sk_buff_head res_q;
struct mt76_queue q_rx;
struct mt76x2_queue q_rx;
u32 msg_seq;
};
struct mt76_rx_freq_cal {
struct mt76x2_rx_freq_cal {
s8 high_gain[MT_MAX_CHAINS];
s8 rssi_offset[MT_MAX_CHAINS];
s8 lna_gain;
u32 mcu_gain;
};
struct mt76_calibration {
struct mt76_rx_freq_cal rx;
struct mt76x2_calibration {
struct mt76x2_rx_freq_cal rx;
u8 agc_gain_init[MT_MAX_CHAINS];
int avg_rssi[MT_MAX_CHAINS];
@@ -127,7 +127,7 @@ struct mt76_calibration {
bool channel_cal_done;
};
struct mt76_wcid {
struct mt76x2_wcid {
u8 idx;
u8 hw_key_idx;
@@ -136,12 +136,12 @@ struct mt76_wcid {
u8 tx_rate_nss;
};
struct mt76_hw_cap {
struct mt76x2_hw_cap {
bool has_2ghz;
bool has_5ghz;
};
struct mt76_rate_power {
struct mt76x2_rate_power {
union {
struct {
s8 cck[4];
@@ -153,21 +153,21 @@ struct mt76_rate_power {
};
};
struct mt76_dma_ops {
int (*queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
struct sk_buff *skb, struct mt76_wcid *wcid,
struct mt76x2_dma_ops {
int (*queue_skb)(struct mt76x2_dev *dev, struct mt76x2_queue *q,
struct sk_buff *skb, struct mt76x2_wcid *wcid,
struct ieee80211_sta *sta);
int (*queue_mcu)(struct mt76_dev *dev, enum mt76_txq_id qid,
int (*queue_mcu)(struct mt76x2_dev *dev, enum mt76x2_txq_id qid,
struct sk_buff *skb, int cmd, int seq);
void (*cleanup_idx)(struct mt76_dev *dev, struct mt76_queue *q, int idx,
void (*cleanup_idx)(struct mt76x2_dev *dev, struct mt76x2_queue *q, int idx,
bool flush, bool *schedule);
int (*add_rx_buf)(struct mt76_dev *dev, struct mt76_queue *q,
int (*add_rx_buf)(struct mt76x2_dev *dev, struct mt76x2_queue *q,
dma_addr_t addr, int len);
};
struct mt76_dev {
struct mt76x2_dev {
struct ieee80211_hw *hw;
struct device *dev;
u8 macaddr[ETH_ALEN];
@@ -177,7 +177,7 @@ struct mt76_dev {
struct mutex mutex;
const struct mt76_dma_ops *dma_ops;
const struct mt76x2_dma_ops *dma_ops;
const u16 *beacon_offsets;
unsigned long wcid_mask[256 / BITS_PER_LONG];
@@ -189,12 +189,12 @@ struct mt76_dev {
int txpower_cur;
u8 txdone_seq;
DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76_tx_status);
DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x2_tx_status);
struct list_head txwi_cache;
struct mt76_mcu mcu;
struct mt76_queue q_rx;
struct mt76_queue q_tx[__MT_TXQ_MAX];
struct mt76x2_mcu mcu;
struct mt76x2_queue q_rx;
struct mt76x2_queue q_tx[__MT_TXQ_MAX];
struct net_device napi_dev;
struct napi_struct napi;
@@ -207,7 +207,7 @@ struct mt76_dev {
u32 aggr_stats[32];
struct mt76_wcid __rcu *wcid[254 - 8];
struct mt76x2_wcid __rcu *wcid[254 - 8];
spinlock_t lock;
spinlock_t irq_lock;
@@ -223,38 +223,38 @@ struct mt76_dev {
u16 chainmask;
struct mt76_calibration cal;
struct mt76x2_calibration cal;
struct debugfs_blob_wrapper eeprom;
struct debugfs_blob_wrapper otp;
struct mt76_hw_cap cap;
struct mt76x2_hw_cap cap;
u32 debugfs_reg;
s8 target_power;
s8 target_power_delta[2];
struct mt76_rate_power rate_power;
struct mt76x2_rate_power rate_power;
u8 coverage_class;
u8 slottime;
};
struct mt76_vif {
struct mt76x2_vif {
u8 idx;
struct mt76_wcid group_wcid;
struct mt76x2_wcid group_wcid;
};
struct mt76_sta {
struct mt76_wcid wcid;
struct mt76x2_sta {
struct mt76x2_wcid wcid;
struct mt76_tx_status status;
struct mt76x2_tx_status status;
int n_frames;
bool sleeping;
};
struct mt76_txq {
struct mt76x2_txq {
struct list_head list;
struct mt76_queue *hwq;
struct mt76x2_queue *hwq;
struct sk_buff_head retry_q;
@@ -263,125 +263,125 @@ struct mt76_txq {
bool aggr;
};
struct mt76_reg_pair {
struct mt76x2_reg_pair {
u32 reg;
u32 value;
};
u32 mt76_rr(struct mt76_dev *dev, u32 offset);
void mt76_wr(struct mt76_dev *dev, u32 offset, u32 val);
u32 mt76_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
void mt76_wr_copy(struct mt76_dev *dev, u32 offset, const void *data, int len);
u32 mt76x2_rr(struct mt76x2_dev *dev, u32 offset);
void mt76x2_wr(struct mt76x2_dev *dev, u32 offset, u32 val);
u32 mt76x2_rmw(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val);
void mt76x2_wr_copy(struct mt76x2_dev *dev, u32 offset, const void *data, int len);
bool mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
bool mt76x2_poll(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
int timeout);
bool mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
bool mt76x2_poll_msec(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val,
int timeout);
void mt76_write_reg_pairs(struct mt76_dev *dev,
const struct mt76_reg_pair *data, int len);
void mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
const struct mt76x2_reg_pair *data, int len);
#define mt76_get_field(_dev, _reg, _field) \
MT76_GET(_field, mt76_rr(dev, _reg))
#define mt76x2_get_field(_dev, _reg, _field) \
MT76_GET(_field, mt76x2_rr(dev, _reg))
#define mt76_rmw_field(_dev, _reg, _field, _val) \
mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
#define mt76x2_rmw_field(_dev, _reg, _field, _val) \
mt76x2_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
static inline u32 mt76_set(struct mt76_dev *dev, u32 offset, u32 val)
static inline u32 mt76x2_set(struct mt76x2_dev *dev, u32 offset, u32 val)
{
return mt76_rmw(dev, offset, 0, val);
return mt76x2_rmw(dev, offset, 0, val);
}
static inline u32 mt76_clear(struct mt76_dev *dev, u32 offset, u32 val)
static inline u32 mt76x2_clear(struct mt76x2_dev *dev, u32 offset, u32 val)
{
return mt76_rmw(dev, offset, val, 0);
return mt76x2_rmw(dev, offset, val, 0);
}
static inline bool is_mt7612(struct mt76_dev *dev)
static inline bool is_mt7612(struct mt76x2_dev *dev)
{
return (dev->rev >> 16) == 0x7612;
}
static inline u16 mt76xx_rev(struct mt76_dev *dev)
static inline u16 mt76xx_rev(struct mt76x2_dev *dev)
{
return dev->rev & 0xffff;
}
void mt76_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set);
void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set);
static inline void mt76_irq_enable(struct mt76_dev *dev, u32 mask)
static inline void mt76x2_irq_enable(struct mt76x2_dev *dev, u32 mask)
{
mt76_set_irq_mask(dev, 0, mask);
mt76x2_set_irq_mask(dev, 0, mask);
}
static inline void mt76_irq_disable(struct mt76_dev *dev, u32 mask)
static inline void mt76x2_irq_disable(struct mt76x2_dev *dev, u32 mask)
{
mt76_set_irq_mask(dev, mask, 0);
mt76x2_set_irq_mask(dev, mask, 0);
}
static inline struct ieee80211_txq *
mtxq_to_txq(struct mt76_txq *mtxq)
mtxq_to_txq(struct mt76x2_txq *mtxq)
{
void *ptr = mtxq;
return container_of(ptr, struct ieee80211_txq, drv_priv);
}
extern const struct ieee80211_ops mt76_ops;
extern const struct ieee80211_ops mt76x2_ops;
struct mt76_dev *mt76_alloc_device(struct device *pdev);
int mt76_register_device(struct mt76_dev *dev);
void mt76_init_debugfs(struct mt76_dev *dev);
struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev);
int mt76x2_register_device(struct mt76x2_dev *dev);
void mt76x2_init_debugfs(struct mt76x2_dev *dev);
irqreturn_t mt76_irq_handler(int irq, void *dev_instance);
void mt76_phy_power_on(struct mt76_dev *dev);
int mt76_init_hardware(struct mt76_dev *dev);
void mt76_stop_hardware(struct mt76_dev *dev);
int mt76_eeprom_init(struct mt76_dev *dev);
int mt76_apply_calibration_data(struct mt76_dev *dev, int channel);
void mt76_set_tx_ackto(struct mt76_dev *dev);
irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance);
void mt76x2_phy_power_on(struct mt76x2_dev *dev);
int mt76x2_init_hardware(struct mt76x2_dev *dev);
void mt76x2_stop_hardware(struct mt76x2_dev *dev);
int mt76x2_eeprom_init(struct mt76x2_dev *dev);
int mt76x2_apply_calibration_data(struct mt76x2_dev *dev, int channel);
void mt76x2_set_tx_ackto(struct mt76x2_dev *dev);
int mt76_phy_start(struct mt76_dev *dev);
int mt76_set_channel(struct mt76_dev *dev, struct cfg80211_chan_def *chandef);
int mt76_phy_set_channel(struct mt76_dev *dev,
int mt76x2_phy_start(struct mt76x2_dev *dev);
int mt76x2_set_channel(struct mt76x2_dev *dev, struct cfg80211_chan_def *chandef);
int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
struct cfg80211_chan_def *chandef);
int mt76_phy_get_rssi(struct mt76_dev *dev, s8 rssi, int chain);
void mt76_phy_calibrate(struct work_struct *work);
void mt76_phy_set_txpower(struct mt76_dev *dev);
int mt76x2_phy_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain);
void mt76x2_phy_calibrate(struct work_struct *work);
void mt76x2_phy_set_txpower(struct mt76x2_dev *dev);
int mt76_mcu_init(struct mt76_dev *dev);
int mt76_mcu_set_channel(struct mt76_dev *dev, u8 channel, u8 bw, u8 bw_index,
int mt76x2_mcu_init(struct mt76x2_dev *dev);
int mt76x2_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw, u8 bw_index,
bool scan);
int mt76_mcu_set_radio_state(struct mt76_dev *dev, bool on);
int mt76_mcu_load_cr(struct mt76_dev *dev, u8 type, u8 temp_level, u8 channel);
int mt76_mcu_cleanup(struct mt76_dev *dev);
int mt76x2_mcu_set_radio_state(struct mt76x2_dev *dev, bool on);
int mt76x2_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level, u8 channel);
int mt76x2_mcu_cleanup(struct mt76x2_dev *dev);
int mt76_dma_init(struct mt76_dev *dev);
void mt76_dma_cleanup(struct mt76_dev *dev);
int mt76x2_dma_init(struct mt76x2_dev *dev);
void mt76x2_dma_cleanup(struct mt76x2_dev *dev);
void mt76_cleanup(struct mt76_dev *dev);
void mt76_rx(struct mt76_dev *dev, struct sk_buff *skb);
void mt76x2_cleanup(struct mt76x2_dev *dev);
void mt76x2_rx(struct mt76x2_dev *dev, struct sk_buff *skb);
#define mt76_tx_queue_skb(dev, ...) dev->dma_ops->queue_skb(dev, __VA_ARGS__)
#define mt76_tx_queue_mcu(dev, ...) dev->dma_ops->queue_mcu(dev, __VA_ARGS__)
#define mt76x2_tx_queue_skb(dev, ...) dev->dma_ops->queue_skb(dev, __VA_ARGS__)
#define mt76x2_tx_queue_mcu(dev, ...) dev->dma_ops->queue_mcu(dev, __VA_ARGS__)
void mt76_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
void mt76x2_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
struct sk_buff *skb);
void mt76_tx_complete(struct mt76_dev *dev, struct sk_buff *skb);
void mt76x2_tx_complete(struct mt76x2_dev *dev, struct sk_buff *skb);
void mt76_kick_queue(struct mt76_dev *dev, struct mt76_queue *q);
void mt76x2_kick_queue(struct mt76x2_dev *dev, struct mt76x2_queue *q);
void mt76_pre_tbtt_tasklet(unsigned long data);
void mt76x2_pre_tbtt_tasklet(unsigned long data);
void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq);
void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq);
void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq);
void mt76x2_txq_init(struct mt76x2_dev *dev, struct ieee80211_txq *txq);
void mt76x2_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
void mt76x2_txq_remove(struct mt76x2_dev *dev, struct ieee80211_txq *txq);
void mt76x2_txq_schedule(struct mt76x2_dev *dev, struct mt76x2_queue *hwq);
void mt76_release_buffered_frames(struct ieee80211_hw *hw,
void mt76x2_release_buffered_frames(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
u16 tids, int nframes,
enum ieee80211_frame_release_type reason,
bool more_data);
void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta);
void mt76x2_stop_tx_queues(struct mt76x2_dev *dev, struct ieee80211_sta *sta);
#endif
of.c
+4 -4
View File
@@ -18,7 +18,7 @@
#include "eeprom.h"
#include "of.h"
static int mt76_check_eeprom(struct mt76_dev *dev, const char *type)
static int mt76x2_check_eeprom(struct mt76x2_dev *dev, const char *type)
{
u16 val = get_unaligned_le16(dev->eeprom.data);
switch (val) {
@@ -32,7 +32,7 @@ static int mt76_check_eeprom(struct mt76_dev *dev, const char *type)
}
int
mt76_get_of_eeprom(struct mt76_dev *dev, int len)
mt76x2_get_of_eeprom(struct mt76x2_dev *dev, int len)
{
struct device_node *np = dev->dev->of_node;
struct mtd_info *mtd;
@@ -79,11 +79,11 @@ mt76_get_of_eeprom(struct mt76_dev *dev, int len)
if (retlen < len)
return -EINVAL;
return mt76_check_eeprom(dev, "Flash");
return mt76x2_check_eeprom(dev, "Flash");
}
void
mt76_get_of_overrides(struct mt76_dev *dev)
mt76x2_get_of_overrides(struct mt76x2_dev *dev)
{
struct device_node *np = dev->dev->of_node;
const __be32 *val;
of.h
+4 -4
View File
@@ -18,19 +18,19 @@
#ifdef CONFIG_OF
int mt76_get_of_eeprom(struct mt76_dev *dev, int len);
void mt76_get_of_overrides(struct mt76_dev *dev);
int mt76x2_get_of_eeprom(struct mt76x2_dev *dev, int len);
void mt76x2_get_of_overrides(struct mt76x2_dev *dev);
#else
static inline int
mt76_get_of_eeprom(struct mt76_dev *dev, int len)
mt76x2_get_of_eeprom(struct mt76x2_dev *dev, int len)
{
return -ENOENT;
}
static inline void
mt76_get_of_overrides(struct mt76_dev *dev)
mt76x2_get_of_overrides(struct mt76x2_dev *dev)
{
}
pci.c
+16 -16
View File
@@ -23,7 +23,7 @@ static const struct pci_device_id mt76pci_device_table[] = {
{ },
};
u32 mt76_rr(struct mt76_dev *dev, u32 offset)
u32 mt76x2_rr(struct mt76x2_dev *dev, u32 offset)
{
u32 val;
@@ -33,20 +33,20 @@ u32 mt76_rr(struct mt76_dev *dev, u32 offset)
return val;
}
void mt76_wr(struct mt76_dev *dev, u32 offset, u32 val)
void mt76x2_wr(struct mt76x2_dev *dev, u32 offset, u32 val)
{
trace_reg_write(dev, offset, val);
iowrite32(val, dev->regs + offset);
}
u32 mt76_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
u32 mt76x2_rmw(struct mt76x2_dev *dev, u32 offset, u32 mask, u32 val)
{
val |= mt76_rr(dev, offset) & ~mask;
mt76_wr(dev, offset, val);
val |= mt76x2_rr(dev, offset) & ~mask;
mt76x2_wr(dev, offset, val);
return val;
}
void mt76_wr_copy(struct mt76_dev *dev, u32 offset, const void *data, int len)
void mt76x2_wr_copy(struct mt76x2_dev *dev, u32 offset, const void *data, int len)
{
__iowrite32_copy(dev->regs + offset, data, len >> 2);
}
@@ -54,7 +54,7 @@ void mt76_wr_copy(struct mt76_dev *dev, u32 offset, const void *data, int len)
static int
mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct mt76_dev *dev;
struct mt76x2_dev *dev;
int ret;
ret = pcim_enable_device(pdev);
@@ -71,7 +71,7 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (ret)
return ret;
dev = mt76_alloc_device(&pdev->dev);
dev = mt76x2_alloc_device(&pdev->dev);
if (!dev)
return -ENOMEM;
@@ -79,28 +79,28 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
pci_set_drvdata(pdev, dev);
dev->rev = mt76_rr(dev, MT_ASIC_VERSION);
dev->rev = mt76x2_rr(dev, MT_ASIC_VERSION);
dev_printk(KERN_INFO, dev->dev, "ASIC revision: %08x\n", dev->rev);
ret = devm_request_irq(dev->dev, pdev->irq, mt76_irq_handler,
ret = devm_request_irq(dev->dev, pdev->irq, mt76x2_irq_handler,
IRQF_SHARED, KBUILD_MODNAME, dev);
if (ret)
goto error;
ret = mt76_register_device(dev);
ret = mt76x2_register_device(dev);
if (ret)
goto error;
/* Fix up ASPM configuration */
/* RG_SSUSB_G1_CDR_BIR_LTR = 0x9 */
mt76_rmw_field(dev, 0x15a10, 0x1f << 16, 0x9);
mt76x2_rmw_field(dev, 0x15a10, 0x1f << 16, 0x9);
/* RG_SSUSB_G1_CDR_BIC_LTR = 0xf */
mt76_rmw_field(dev, 0x15a0c, 0xf << 28, 0xf);
mt76x2_rmw_field(dev, 0x15a0c, 0xf << 28, 0xf);
/* RG_SSUSB_CDR_BR_PE1D = 0x3 */
mt76_rmw_field(dev, 0x15c58, 0x3 << 6, 0x3);
mt76x2_rmw_field(dev, 0x15c58, 0x3 << 6, 0x3);
return 0;
@@ -112,10 +112,10 @@ error:
static void
mt76pci_remove(struct pci_dev *pdev)
{
struct mt76_dev *dev = pci_get_drvdata(pdev);
struct mt76x2_dev *dev = pci_get_drvdata(pdev);
ieee80211_unregister_hw(dev->hw);
mt76_cleanup(dev);
mt76x2_cleanup(dev);
ieee80211_free_hw(dev->hw);
printk("pci device driver detached\n");
}
phy.c
+190 -190
View File
@@ -17,7 +17,7 @@
#include "eeprom.h"
static bool
mt76_phy_rf_op(struct mt76_dev *dev, bool idx, u16 offset, bool write)
mt76x2_phy_rf_op(struct mt76x2_dev *dev, bool idx, u16 offset, bool write)
{
u32 val = MT76_SET(MT_RF_CTRL_ADDR, offset);
@@ -27,66 +27,66 @@ mt76_phy_rf_op(struct mt76_dev *dev, bool idx, u16 offset, bool write)
if (write)
val |= MT_RF_CTRL_WRITE;
mt76_wr(dev, MT_RF_CTRL, val);
mt76x2_wr(dev, MT_RF_CTRL, val);
return mt76_poll(dev, MT_RF_CTRL, MT_RF_CTRL_BUSY, 0, 2000);
return mt76x2_poll(dev, MT_RF_CTRL, MT_RF_CTRL_BUSY, 0, 2000);
}
static int __maybe_unused
mt76_phy_rf_read(struct mt76_dev *dev, bool idx, u16 offset, u32 *val)
mt76x2_phy_rf_read(struct mt76x2_dev *dev, bool idx, u16 offset, u32 *val)
{
if (!mt76_phy_rf_op(dev, idx, offset, false))
if (!mt76x2_phy_rf_op(dev, idx, offset, false))
return -ETIMEDOUT;
*val = mt76_rr(dev, MT_RF_DATA_READ);
*val = mt76x2_rr(dev, MT_RF_DATA_READ);
return 0;
}
static int __maybe_unused
mt76_phy_rf_write(struct mt76_dev *dev, bool idx, u16 offset, u32 val)
mt76x2_phy_rf_write(struct mt76x2_dev *dev, bool idx, u16 offset, u32 val)
{
mt76_wr(dev, MT_RF_DATA_WRITE, val);
mt76x2_wr(dev, MT_RF_DATA_WRITE, val);
if (!mt76_phy_rf_op(dev, idx, offset, true))
if (!mt76x2_phy_rf_op(dev, idx, offset, true))
return -ETIMEDOUT;
return 0;
}
static void
mt76_adjust_lna_gain(struct mt76_dev *dev, int reg, s8 offset)
mt76x2_adjust_lna_gain(struct mt76x2_dev *dev, int reg, s8 offset)
{
s8 gain;
gain = MT76_GET(MT_BBP_AGC_LNA_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
gain = MT76_GET(MT_BBP_AGC_LNA_GAIN, mt76x2_rr(dev, MT_BBP(AGC, reg)));
gain -= offset / 2;
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_GAIN, gain);
mt76x2_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_GAIN, gain);
}
static void
mt76_adjust_agc_gain(struct mt76_dev *dev, int reg, s8 offset)
mt76x2_adjust_agc_gain(struct mt76x2_dev *dev, int reg, s8 offset)
{
s8 gain;
gain = MT76_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
gain = MT76_GET(MT_BBP_AGC_GAIN, mt76x2_rr(dev, MT_BBP(AGC, reg)));
gain += offset;
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
mt76x2_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
}
static void
mt76_apply_gain_adj(struct mt76_dev *dev)
mt76x2_apply_gain_adj(struct mt76x2_dev *dev)
{
s8 *gain_adj = dev->cal.rx.high_gain;
mt76_adjust_lna_gain(dev, 4, gain_adj[0]);
mt76_adjust_lna_gain(dev, 5, gain_adj[1]);
mt76x2_adjust_lna_gain(dev, 4, gain_adj[0]);
mt76x2_adjust_lna_gain(dev, 5, gain_adj[1]);
mt76_adjust_agc_gain(dev, 8, gain_adj[0]);
mt76_adjust_agc_gain(dev, 9, gain_adj[1]);
mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]);
mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]);
}
static u32
mt76_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
mt76x2_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
{
u32 val = 0;
@@ -97,9 +97,9 @@ mt76_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
return val;
}
int mt76_phy_get_rssi(struct mt76_dev *dev, s8 rssi, int chain)
int mt76x2_phy_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain)
{
struct mt76_rx_freq_cal *cal = &dev->cal.rx;
struct mt76x2_rx_freq_cal *cal = &dev->cal.rx;
rssi += cal->rssi_offset[chain];
rssi -= cal->lna_gain;
@@ -108,7 +108,7 @@ int mt76_phy_get_rssi(struct mt76_dev *dev, s8 rssi, int chain)
}
static u8
mt76_txpower_check(int value)
mt76x2_txpower_check(int value)
{
if (value < 0)
return 0;
@@ -118,7 +118,7 @@ mt76_txpower_check(int value)
}
static void
mt76_add_rate_power_offset(struct mt76_rate_power *r, int offset)
mt76x2_add_rate_power_offset(struct mt76x2_rate_power *r, int offset)
{
int i;
@@ -127,7 +127,7 @@ mt76_add_rate_power_offset(struct mt76_rate_power *r, int offset)
}
static void
mt76_limit_rate_power(struct mt76_rate_power *r, int limit)
mt76x2_limit_rate_power(struct mt76x2_rate_power *r, int limit)
{
int i;
@@ -137,7 +137,7 @@ mt76_limit_rate_power(struct mt76_rate_power *r, int limit)
}
static int
mt76_get_max_power(struct mt76_rate_power *r)
mt76x2_get_max_power(struct mt76x2_rate_power *r)
{
int i;
s8 ret = 0;
@@ -148,14 +148,14 @@ mt76_get_max_power(struct mt76_rate_power *r)
return ret;
}
void mt76_phy_set_txpower(struct mt76_dev *dev)
void mt76x2_phy_set_txpower(struct mt76x2_dev *dev)
{
enum nl80211_chan_width width = dev->chandef.width;
struct mt76_tx_power_info txp;
struct mt76x2_tx_power_info txp;
int txp_0, txp_1, delta = 0;
struct mt76_rate_power t = {};
struct mt76x2_rate_power t = {};
mt76_get_power_info(dev, &txp);
mt76x2_get_power_info(dev, &txp);
if (width == NL80211_CHAN_WIDTH_40)
delta = txp.delta_bw40;
@@ -165,47 +165,47 @@ void mt76_phy_set_txpower(struct mt76_dev *dev)
if (txp.target_power > dev->txpower_conf)
delta -= txp.target_power - dev->txpower_conf;
mt76_get_rate_power(dev, &t);
mt76_add_rate_power_offset(&t, txp.chain[0].target_power +
mt76x2_get_rate_power(dev, &t);
mt76x2_add_rate_power_offset(&t, txp.chain[0].target_power +
txp.chain[0].delta);
mt76_limit_rate_power(&t, dev->txpower_conf);
dev->txpower_cur = mt76_get_max_power(&t);
mt76_add_rate_power_offset(&t, -(txp.chain[0].target_power +
mt76x2_limit_rate_power(&t, dev->txpower_conf);
dev->txpower_cur = mt76x2_get_max_power(&t);
mt76x2_add_rate_power_offset(&t, -(txp.chain[0].target_power +
txp.chain[0].delta + delta));
dev->target_power = txp.chain[0].target_power;
dev->target_power_delta[0] = txp.chain[0].delta + delta;
dev->target_power_delta[1] = txp.chain[1].delta + delta;
dev->rate_power = t;
txp_0 = mt76_txpower_check(txp.chain[0].target_power +
txp_0 = mt76x2_txpower_check(txp.chain[0].target_power +
txp.chain[0].delta + delta);
txp_1 = mt76_txpower_check(txp.chain[1].target_power +
txp_1 = mt76x2_txpower_check(txp.chain[1].target_power +
txp.chain[1].delta + delta);
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
mt76x2_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
mt76x2_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
mt76_wr(dev, MT_TX_PWR_CFG_0,
mt76_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
mt76_wr(dev, MT_TX_PWR_CFG_1,
mt76_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[2]));
mt76_wr(dev, MT_TX_PWR_CFG_2,
mt76_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
mt76_wr(dev, MT_TX_PWR_CFG_3,
mt76_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
mt76_wr(dev, MT_TX_PWR_CFG_4,
mt76_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
mt76_wr(dev, MT_TX_PWR_CFG_7,
mt76_tx_power_mask(t.ofdm[4], t.vht[8], t.ht[6], t.vht[8]));
mt76_wr(dev, MT_TX_PWR_CFG_8,
mt76_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
mt76_wr(dev, MT_TX_PWR_CFG_9,
mt76_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
mt76x2_wr(dev, MT_TX_PWR_CFG_0,
mt76x2_tx_power_mask(t.cck[0], t.cck[2], t.ofdm[0], t.ofdm[2]));
mt76x2_wr(dev, MT_TX_PWR_CFG_1,
mt76x2_tx_power_mask(t.ofdm[4], t.ofdm[6], t.ht[0], t.ht[2]));
mt76x2_wr(dev, MT_TX_PWR_CFG_2,
mt76x2_tx_power_mask(t.ht[4], t.ht[6], t.ht[8], t.ht[10]));
mt76x2_wr(dev, MT_TX_PWR_CFG_3,
mt76x2_tx_power_mask(t.ht[12], t.ht[14], t.ht[0], t.ht[2]));
mt76x2_wr(dev, MT_TX_PWR_CFG_4,
mt76x2_tx_power_mask(t.ht[4], t.ht[6], 0, 0));
mt76x2_wr(dev, MT_TX_PWR_CFG_7,
mt76x2_tx_power_mask(t.ofdm[4], t.vht[8], t.ht[6], t.vht[8]));
mt76x2_wr(dev, MT_TX_PWR_CFG_8,
mt76x2_tx_power_mask(t.ht[14], t.vht[8], t.vht[8], 0));
mt76x2_wr(dev, MT_TX_PWR_CFG_9,
mt76x2_tx_power_mask(t.ht[6], t.vht[8], t.vht[8], 0));
}
static bool
mt76_channel_silent(struct mt76_dev *dev)
mt76x2_channel_silent(struct mt76x2_dev *dev)
{
struct ieee80211_channel *chan = dev->chandef.chan;
@@ -214,30 +214,30 @@ mt76_channel_silent(struct mt76_dev *dev)
}
static bool
mt76_phy_tssi_init_cal(struct mt76_dev *dev)
mt76x2_phy_tssi_init_cal(struct mt76x2_dev *dev)
{
struct ieee80211_channel *chan = dev->chandef.chan;
u32 flag = 0;
if (!mt76_tssi_enabled(dev))
if (!mt76x2_tssi_enabled(dev))
return false;
if (mt76_channel_silent(dev))
if (mt76x2_channel_silent(dev))
return false;
if (chan->band == IEEE80211_BAND_2GHZ)
flag |= BIT(0);
if (mt76_ext_pa_enabled(dev, chan->band))
if (mt76x2_ext_pa_enabled(dev, chan->band))
flag |= BIT(8);
mt76_mcu_calibrate(dev, MCU_CAL_TSSI, flag);
mt76x2_mcu_calibrate(dev, MCU_CAL_TSSI, flag);
dev->cal.tssi_cal_done = true;
return true;
}
static void
mt76_phy_channel_calibrate(struct mt76_dev *dev, bool mac_stopped)
mt76x2_phy_channel_calibrate(struct mt76x2_dev *dev, bool mac_stopped)
{
struct ieee80211_channel *chan = dev->chandef.chan;
bool is_5ghz = chan->band == IEEE80211_BAND_5GHZ;
@@ -245,34 +245,34 @@ mt76_phy_channel_calibrate(struct mt76_dev *dev, bool mac_stopped)
if (dev->cal.channel_cal_done)
return;
if (mt76_channel_silent(dev))
if (mt76x2_channel_silent(dev))
return;
if (!dev->cal.tssi_cal_done)
mt76_phy_tssi_init_cal(dev);
mt76x2_phy_tssi_init_cal(dev);
if (!mac_stopped)
mt76_mac_stop(dev, false);
mt76x2_mac_stop(dev, false);
if (is_5ghz)
mt76_mcu_calibrate(dev, MCU_CAL_LC, 0);
mt76x2_mcu_calibrate(dev, MCU_CAL_LC, 0);
mt76_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz);
mt76_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
mt76_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz);
mt76_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0);
mt76_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0);
mt76x2_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz);
mt76x2_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
mt76x2_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz);
mt76x2_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0);
mt76x2_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0);
if (!mac_stopped)
mt76_mac_resume(dev);
mt76x2_mac_resume(dev);
mt76_apply_gain_adj(dev);
mt76x2_apply_gain_adj(dev);
dev->cal.channel_cal_done = true;
}
static void
mt76_phy_set_txpower_regs(struct mt76_dev *dev, enum ieee80211_band band)
mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev, enum ieee80211_band band)
{
u32 pa_mode[2];
u32 pa_mode_adj;
@@ -281,78 +281,78 @@ mt76_phy_set_txpower_regs(struct mt76_dev *dev, enum ieee80211_band band)
pa_mode[0] = 0x010055ff;
pa_mode[1] = 0x00550055;
mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
mt76x2_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
mt76x2_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
if (mt76_ext_pa_enabled(dev, band)) {
mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
if (mt76x2_ext_pa_enabled(dev, band)) {
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
} else {
mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
}
} else {
pa_mode[0] = 0x0000ffff;
pa_mode[1] = 0x00ff00ff;
mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
mt76x2_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
mt76x2_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0);
if (mt76_ext_pa_enabled(dev, band))
if (mt76x2_ext_pa_enabled(dev, band))
pa_mode_adj = 0x04000000;
else
pa_mode_adj = 0;
mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
mt76x2_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
}
mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
mt76x2_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
mt76x2_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
mt76x2_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
mt76x2_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
if (mt76_ext_pa_enabled(dev, band)) {
if (mt76x2_ext_pa_enabled(dev, band)) {
u32 val = 0x3c3c023c;
mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, val);
mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, val);
mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
} else {
if (band == IEEE80211_BAND_2GHZ) {
u32 val = 0x0f3c3c3c;
mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, val);
mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, val);
mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
} else {
mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
mt76x2_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
mt76x2_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
mt76x2_wr(dev, MT_TX_ALC_CFG_4, 0);
}
}
}
static void
mt76_configure_tx_delay(struct mt76_dev *dev, enum ieee80211_band band, u8 bw)
mt76x2_configure_tx_delay(struct mt76x2_dev *dev, enum ieee80211_band band, u8 bw)
{
u32 cfg0, cfg1;
if (mt76_ext_pa_enabled(dev, band)) {
if (mt76x2_ext_pa_enabled(dev, band)) {
cfg0 = bw ? 0x000b0c01 : 0x00101101;
cfg1 = 0x00011414;
} else {
cfg0 = bw ? 0x000b0b01 : 0x00101001;
cfg1 = 0x00021414;
}
mt76_wr(dev, MT_TX_SW_CFG0, cfg0);
mt76_wr(dev, MT_TX_SW_CFG1, cfg1);
mt76x2_wr(dev, MT_TX_SW_CFG0, cfg0);
mt76x2_wr(dev, MT_TX_SW_CFG1, cfg1);
mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_CCK_SIFS,
mt76x2_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_CCK_SIFS,
13 + (bw ? 1 : 0));
}
static void
mt76_phy_set_bw(struct mt76_dev *dev, int width, u8 ctrl)
mt76x2_phy_set_bw(struct mt76x2_dev *dev, int width, u8 ctrl)
{
int core_val, agc_val;
@@ -371,62 +371,62 @@ mt76_phy_set_bw(struct mt76_dev *dev, int width, u8 ctrl)
break;
}
mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
mt76x2_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
mt76x2_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
mt76x2_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
mt76x2_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
}
static void
mt76_phy_set_band(struct mt76_dev *dev, int band, bool primary_upper)
mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper)
{
switch (band) {
case IEEE80211_BAND_2GHZ:
mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
mt76x2_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76x2_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
break;
case IEEE80211_BAND_5GHZ:
mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
mt76x2_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
mt76x2_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
break;
}
mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
mt76x2_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
primary_upper);
}
static void
mt76_set_rx_chains(struct mt76_dev *dev)
mt76x2_set_rx_chains(struct mt76x2_dev *dev)
{
u32 val;
val = mt76_rr(dev, MT_BBP(AGC, 0));
val = mt76x2_rr(dev, MT_BBP(AGC, 0));
val &= ~(BIT(3) | BIT(4));
if (dev->chainmask & BIT(1))
val |= BIT(3);
mt76_wr(dev, MT_BBP(AGC, 0), val);
mt76x2_wr(dev, MT_BBP(AGC, 0), val);
}
static void
mt76_set_tx_dac(struct mt76_dev *dev)
mt76x2_set_tx_dac(struct mt76x2_dev *dev)
{
if (dev->chainmask & BIT(1))
mt76_set(dev, MT_BBP(TXBE, 5), 3);
mt76x2_set(dev, MT_BBP(TXBE, 5), 3);
else
mt76_clear(dev, MT_BBP(TXBE, 5), 3);
mt76x2_clear(dev, MT_BBP(TXBE, 5), 3);
}
static void
mt76_get_agc_gain(struct mt76_dev *dev, u8 *dest)
mt76x2_get_agc_gain(struct mt76x2_dev *dev, u8 *dest)
{
dest[0] = mt76_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
dest[1] = mt76_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
dest[0] = mt76x2_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
dest[1] = mt76x2_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
}
static int
mt76_get_rssi_gain_thresh(struct mt76_dev *dev)
mt76x2_get_rssi_gain_thresh(struct mt76x2_dev *dev)
{
switch (dev->chandef.width) {
case NL80211_CHAN_WIDTH_80:
@@ -439,9 +439,9 @@ mt76_get_rssi_gain_thresh(struct mt76_dev *dev)
}
static void
mt76_phy_update_channel_gain(struct mt76_dev *dev)
mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
{
u32 val = mt76_rr(dev, MT_BBP(AGC, 20));
u32 val = mt76x2_rr(dev, MT_BBP(AGC, 20));
int rssi0 = (s8) MT76_GET(MT_BBP_AGC20_RSSI0, val);
int rssi1 = (s8) MT76_GET(MT_BBP_AGC20_RSSI1, val);
bool low_gain;
@@ -451,7 +451,7 @@ mt76_phy_update_channel_gain(struct mt76_dev *dev)
dev->cal.avg_rssi[1] = (dev->cal.avg_rssi[1] * 15) / 16 + (rssi1 << 8);
dev->cal.avg_rssi_all = (dev->cal.avg_rssi[0] + dev->cal.avg_rssi[1]) / 512;
low_gain = dev->cal.avg_rssi_all > mt76_get_rssi_gain_thresh(dev);
low_gain = dev->cal.avg_rssi_all > mt76x2_get_rssi_gain_thresh(dev);
if (dev->cal.low_gain == low_gain)
return;
@@ -465,30 +465,30 @@ mt76_phy_update_channel_gain(struct mt76_dev *dev)
val |= 0xf8;
if (dev->chandef.width == NL80211_CHAN_WIDTH_80)
mt76_wr(dev, MT_BBP(RXO, 14), 0x00560411);
mt76x2_wr(dev, MT_BBP(RXO, 14), 0x00560411);
else
mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
mt76x2_wr(dev, MT_BBP(RXO, 14), 0x00560423);
if (low_gain) {
mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
if (mt76_has_ext_lna(dev))
mt76x2_wr(dev, MT_BBP(AGC, 35), 0x08080808);
mt76x2_wr(dev, MT_BBP(AGC, 37), 0x08080808);
if (mt76x2_has_ext_lna(dev))
gain_delta = 10;
else
gain_delta = 14;
} else {
mt76_wr(dev, MT_BBP(AGC, 35), 0x11111116);
mt76_wr(dev, MT_BBP(AGC, 37), 0x1010161C);
mt76x2_wr(dev, MT_BBP(AGC, 35), 0x11111116);
mt76x2_wr(dev, MT_BBP(AGC, 37), 0x1010161C);
gain_delta = 0;
}
mt76_wr(dev, MT_BBP(AGC, 8),
mt76x2_wr(dev, MT_BBP(AGC, 8),
val | MT76_SET(MT_BBP_AGC_GAIN, gain[0] - gain_delta));
mt76_wr(dev, MT_BBP(AGC, 9),
mt76x2_wr(dev, MT_BBP(AGC, 9),
val | MT76_SET(MT_BBP_AGC_GAIN, gain[1] - gain_delta));
}
int mt76_phy_set_channel(struct mt76_dev *dev,
int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
struct cfg80211_chan_def *chandef)
{
struct ieee80211_channel *chan = chandef->chan;
@@ -557,17 +557,17 @@ int mt76_phy_set_channel(struct mt76_dev *dev,
break;
}
mt76_read_rx_gain(dev);
mt76_phy_set_txpower_regs(dev, band);
mt76_configure_tx_delay(dev, band, bw);
mt76_phy_set_txpower(dev);
mt76x2_read_rx_gain(dev);
mt76x2_phy_set_txpower_regs(dev, band);
mt76x2_configure_tx_delay(dev, band, bw);
mt76x2_phy_set_txpower(dev);
mt76_set_rx_chains(dev);
mt76_phy_set_band(dev, chan->band, ch_group_index & 1);
mt76_phy_set_bw(dev, chandef->width, ch_group_index);
mt76_set_tx_dac(dev);
mt76x2_set_rx_chains(dev);
mt76x2_phy_set_band(dev, chan->band, ch_group_index & 1);
mt76x2_phy_set_bw(dev, chandef->width, ch_group_index);
mt76x2_set_tx_dac(dev);
mt76_rmw(dev, MT_EXT_CCA_CFG,
mt76x2_rmw(dev, MT_EXT_CCA_CFG,
(MT_EXT_CCA_CFG_CCA0 |
MT_EXT_CCA_CFG_CCA1 |
MT_EXT_CCA_CFG_CCA2 |
@@ -578,45 +578,45 @@ int mt76_phy_set_channel(struct mt76_dev *dev,
if (chandef->width >= NL80211_CHAN_WIDTH_40)
sifs++;
mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs);
mt76x2_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs);
ret = mt76_mcu_set_channel(dev, channel, bw, bw_index, scan);
ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan);
if (ret)
return ret;
mt76_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
mt76x2_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
/* Enable LDPC Rx */
if (mt76xx_rev(dev) >= MT76XX_REV_E3)
mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
mt76x2_set(dev, MT_BBP(RXO, 13), BIT(10));
if (!dev->cal.init_cal_done) {
u8 val = mt76_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
u8 val = mt76x2_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
if (val != 0xff)
mt76_mcu_calibrate(dev, MCU_CAL_R, 0);
mt76x2_mcu_calibrate(dev, MCU_CAL_R, 0);
}
mt76_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
mt76x2_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
/* Rx LPF calibration */
if (!dev->cal.init_cal_done)
mt76_mcu_calibrate(dev, MCU_CAL_RC, 0);
mt76x2_mcu_calibrate(dev, MCU_CAL_RC, 0);
dev->cal.init_cal_done = true;
mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
mt76x2_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
mt76x2_wr(dev, MT_BBP(AGC, 7), 0x08081010);
mt76x2_wr(dev, MT_BBP(AGC, 11), 0x00000404);
mt76x2_wr(dev, MT_BBP(AGC, 2), 0x00007070);
mt76x2_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
if (scan)
return 0;
dev->cal.low_gain = -1;
mt76_phy_channel_calibrate(dev, true);
mt76_get_agc_gain(dev, dev->cal.agc_gain_init);
mt76x2_phy_channel_calibrate(dev, true);
mt76x2_get_agc_gain(dev, dev->cal.agc_gain_init);
ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
MT_CALIBRATE_INTERVAL);
@@ -625,11 +625,11 @@ int mt76_phy_set_channel(struct mt76_dev *dev,
}
static void
mt76_phy_tssi_compensate(struct mt76_dev *dev)
mt76x2_phy_tssi_compensate(struct mt76x2_dev *dev)
{
struct ieee80211_channel *chan = dev->chandef.chan;
struct mt76_tx_power_info txp;
struct mt76_tssi_comp t = {};
struct mt76x2_tx_power_info txp;
struct mt76x2_tssi_comp t = {};
if (!dev->cal.tssi_cal_done)
return;
@@ -637,16 +637,16 @@ mt76_phy_tssi_compensate(struct mt76_dev *dev)
if (!dev->cal.tssi_comp_pending) {
/* TSSI trigger */
t.cal_mode = BIT(0);
mt76_mcu_tssi_comp(dev, &t);
mt76x2_mcu_tssi_comp(dev, &t);
dev->cal.tssi_comp_pending = true;
} else {
if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
if (mt76x2_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
return;
dev->cal.tssi_comp_pending = false;
mt76_get_power_info(dev, &txp);
mt76x2_get_power_info(dev, &txp);
if (mt76_ext_pa_enabled(dev, chan->band))
if (mt76x2_ext_pa_enabled(dev, chan->band))
t.pa_mode = 1;
t.cal_mode = BIT(1);
@@ -654,27 +654,27 @@ mt76_phy_tssi_compensate(struct mt76_dev *dev)
t.offset0 = txp.chain[0].tssi_offset;
t.slope1 = txp.chain[1].tssi_slope;
t.offset1 = txp.chain[1].tssi_offset;
mt76_mcu_tssi_comp(dev, &t);
mt76x2_mcu_tssi_comp(dev, &t);
if (t.pa_mode || dev->cal.dpd_cal_done)
return;
msleep(10);
mt76_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
mt76x2_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
dev->cal.dpd_cal_done = true;
}
}
static void
mt76_phy_temp_compensate(struct mt76_dev *dev)
mt76x2_phy_temp_compensate(struct mt76x2_dev *dev)
{
struct mt76_temp_comp t;
struct mt76x2_temp_comp t;
int temp, db_diff;
if (mt76_get_temp_comp(dev, &t))
if (mt76x2_get_temp_comp(dev, &t))
return;
temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
temp = mt76x2_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
temp -= t.temp_25_ref;
temp = (temp * 1789) / 1000 + 25;
dev->cal.temp = temp;
@@ -687,34 +687,34 @@ mt76_phy_temp_compensate(struct mt76_dev *dev)
db_diff = min(db_diff, t.upper_bound);
db_diff = max(db_diff, t.lower_bound);
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
mt76x2_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
db_diff * 2);
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
mt76x2_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
db_diff * 2);
}
void mt76_phy_calibrate(struct work_struct *work)
void mt76x2_phy_calibrate(struct work_struct *work)
{
struct mt76_dev *dev;
struct mt76x2_dev *dev;
dev = container_of(work, struct mt76_dev, cal_work.work);
mt76_phy_channel_calibrate(dev, false);
mt76_phy_tssi_compensate(dev);
mt76_phy_temp_compensate(dev);
mt76_phy_update_channel_gain(dev);
dev = container_of(work, struct mt76x2_dev, cal_work.work);
mt76x2_phy_channel_calibrate(dev, false);
mt76x2_phy_tssi_compensate(dev);
mt76x2_phy_temp_compensate(dev);
mt76x2_phy_update_channel_gain(dev);
ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
MT_CALIBRATE_INTERVAL);
}
int mt76_phy_start(struct mt76_dev *dev)
int mt76x2_phy_start(struct mt76x2_dev *dev)
{
int ret;
ret = mt76_mcu_set_radio_state(dev, true);
ret = mt76x2_mcu_set_radio_state(dev, true);
if (ret)
return ret;
mt76_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
return ret;
}
regs.h
+4 -4
View File
@@ -512,25 +512,25 @@
#define MT_TEMP_SENSOR 0x1d000
#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)
struct mt76_wcid_addr {
struct mt76x2_wcid_addr {
u8 macaddr[6];
__le16 ba_mask;
} __packed __aligned(4);
struct mt76_wcid_key {
struct mt76x2_wcid_key {
u8 key[16];
u8 tx_mic[8];
u8 rx_mic[8];
} __packed __aligned(4);
struct mt76_queue_regs {
struct mt76x2_queue_regs {
u32 desc_base;
u32 ring_size;
u32 cpu_idx;
u32 dma_idx;
} __packed __aligned(4);
enum mt76_cipher_type {
enum mt76x2_cipher_type {
MT_CIPHER_NONE,
MT_CIPHER_WEP40,
MT_CIPHER_WEP104,
trace.h
+10 -10
View File
@@ -37,7 +37,7 @@
#define REG_PR_ARG __entry->reg, __entry->val
DECLARE_EVENT_CLASS(dev_evt,
TP_PROTO(struct mt76_dev *dev),
TP_PROTO(struct mt76x2_dev *dev),
TP_ARGS(dev),
TP_STRUCT__entry(
DEV_ENTRY
@@ -49,7 +49,7 @@ DECLARE_EVENT_CLASS(dev_evt,
);
DECLARE_EVENT_CLASS(dev_txid_evt,
TP_PROTO(struct mt76_dev *dev, u8 wcid, u8 pktid),
TP_PROTO(struct mt76x2_dev *dev, u8 wcid, u8 pktid),
TP_ARGS(dev, wcid, pktid),
TP_STRUCT__entry(
DEV_ENTRY
@@ -66,7 +66,7 @@ DECLARE_EVENT_CLASS(dev_txid_evt,
);
DECLARE_EVENT_CLASS(dev_reg_evt,
TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
TP_ARGS(dev, reg, val),
TP_STRUCT__entry(
DEV_ENTRY
@@ -83,28 +83,28 @@ DECLARE_EVENT_CLASS(dev_reg_evt,
);
DEFINE_EVENT(dev_reg_evt, reg_read,
TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
TP_ARGS(dev, reg, val)
);
DEFINE_EVENT(dev_reg_evt, reg_write,
TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val),
TP_PROTO(struct mt76x2_dev *dev, u32 reg, u32 val),
TP_ARGS(dev, reg, val)
);
DEFINE_EVENT(dev_evt, mac_txstat_poll,
TP_PROTO(struct mt76_dev *dev),
TP_PROTO(struct mt76x2_dev *dev),
TP_ARGS(dev)
);
DEFINE_EVENT(dev_txid_evt, mac_txdone_add,
TP_PROTO(struct mt76_dev *dev, u8 wcid, u8 pktid),
TP_PROTO(struct mt76x2_dev *dev, u8 wcid, u8 pktid),
TP_ARGS(dev, wcid, pktid)
);
TRACE_EVENT(mac_txstat_fetch,
TP_PROTO(struct mt76_dev *dev,
struct mt76_tx_status *stat),
TP_PROTO(struct mt76x2_dev *dev,
struct mt76x2_tx_status *stat),
TP_ARGS(dev, stat),
@@ -141,7 +141,7 @@ TRACE_EVENT(mac_txstat_fetch,
TRACE_EVENT(dev_irq,
TP_PROTO(struct mt76_dev *dev, u32 val, u32 mask),
TP_PROTO(struct mt76x2_dev *dev, u32 val, u32 mask),
TP_ARGS(dev, val, mask),
tx.c
+81 -81
View File
@@ -14,21 +14,21 @@
#include "mt76.h"
struct beacon_bc_data {
struct mt76_dev *dev;
struct mt76x2_dev *dev;
struct sk_buff_head q;
struct sk_buff *tail[8];
};
void mt76_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
void mt76x2_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
struct ieee80211_vif *vif = info->control.vif;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76_sta *msta = NULL;
struct mt76_wcid *wcid = &mvif->group_wcid;
struct mt76_queue *q;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
struct mt76x2_sta *msta = NULL;
struct mt76x2_wcid *wcid = &mvif->group_wcid;
struct mt76x2_queue *q;
int qid = skb_get_queue_mapping(skb);
if (WARN_ON(qid >= MT_TXQ_PSD)) {
@@ -37,7 +37,7 @@ void mt76_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
}
if (control->sta) {
msta = (struct mt76_sta *) control->sta->drv_priv;
msta = (struct mt76x2_sta *) control->sta->drv_priv;
wcid = &msta->wcid;
}
@@ -48,18 +48,18 @@ void mt76_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
q = &dev->q_tx[qid];
spin_lock_bh(&q->lock);
mt76_tx_queue_skb(dev, q, skb, wcid, control->sta);
mt76_kick_queue(dev, q);
mt76x2_tx_queue_skb(dev, q, skb, wcid, control->sta);
mt76x2_kick_queue(dev, q);
if (q->queued > q->ndesc - 8)
ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
spin_unlock_bh(&q->lock);
}
void mt76_tx_complete(struct mt76_dev *dev, struct sk_buff *skb)
void mt76x2_tx_complete(struct mt76x2_dev *dev, struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct mt76_queue *q;
struct mt76x2_queue *q;
int qid = skb_get_queue_mapping(skb);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
@@ -77,10 +77,10 @@ void mt76_tx_complete(struct mt76_dev *dev, struct sk_buff *skb)
}
static void
mt76_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
mt76x2_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
{
struct mt76_dev *dev = (struct mt76_dev *) priv;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_dev *dev = (struct mt76x2_dev *) priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
struct ieee80211_tx_info *info;
struct sk_buff *skb = NULL;
@@ -93,11 +93,11 @@ mt76_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
info = IEEE80211_SKB_CB(skb);
info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
mt76_mac_set_beacon(dev, mvif->idx, skb);
mt76x2_mac_set_beacon(dev, mvif->idx, skb);
}
static void
mt76_skb_set_moredata(struct sk_buff *skb, bool enable)
mt76x2_skb_set_moredata(struct sk_buff *skb, bool enable)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
@@ -108,11 +108,11 @@ mt76_skb_set_moredata(struct sk_buff *skb, bool enable)
}
static void
mt76_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
mt76x2_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
{
struct beacon_bc_data *data = priv;
struct mt76_dev *dev = data->dev;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_dev *dev = data->dev;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
struct ieee80211_tx_info *info;
struct sk_buff *skb;
@@ -126,15 +126,15 @@ mt76_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
info = IEEE80211_SKB_CB(skb);
info->control.vif = vif;
info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
mt76_skb_set_moredata(skb, true);
mt76x2_skb_set_moredata(skb, true);
__skb_queue_tail(&data->q, skb);
data->tail[mvif->idx] = skb;
}
void mt76_pre_tbtt_tasklet(unsigned long arg)
void mt76x2_pre_tbtt_tasklet(unsigned long arg)
{
struct mt76_dev *dev = (struct mt76_dev *) arg;
struct mt76_queue *q = &dev->q_tx[MT_TXQ_PSD];
struct mt76x2_dev *dev = (struct mt76x2_dev *) arg;
struct mt76x2_queue *q = &dev->q_tx[MT_TXQ_PSD];
struct beacon_bc_data data = {};
struct sk_buff *skb;
int i, nframes;
@@ -144,13 +144,13 @@ void mt76_pre_tbtt_tasklet(unsigned long arg)
ieee80211_iterate_active_interfaces_atomic(dev->hw,
IEEE80211_IFACE_ITER_RESUME_ALL,
mt76_update_beacon_iter, dev);
mt76x2_update_beacon_iter, dev);
do {
nframes = skb_queue_len(&data.q);
ieee80211_iterate_active_interfaces_atomic(dev->hw,
IEEE80211_IFACE_ITER_RESUME_ALL,
mt76_add_buffered_bc, &data);
mt76x2_add_buffered_bc, &data);
} while (nframes != skb_queue_len(&data.q));
if (!nframes)
@@ -160,22 +160,22 @@ void mt76_pre_tbtt_tasklet(unsigned long arg)
if (!data.tail[i])
continue;
mt76_skb_set_moredata(data.tail[i], false);
mt76x2_skb_set_moredata(data.tail[i], false);
}
spin_lock_bh(&q->lock);
while ((skb = __skb_dequeue(&data.q)) != NULL) {
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct ieee80211_vif *vif = info->control.vif;
struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) vif->drv_priv;
mt76_tx_queue_skb(dev, q, skb, &mvif->group_wcid, NULL);
mt76x2_tx_queue_skb(dev, q, skb, &mvif->group_wcid, NULL);
}
spin_unlock_bh(&q->lock);
}
static int
mt76_txq_get_qid(struct ieee80211_txq *txq)
mt76x2_txq_get_qid(struct ieee80211_txq *txq)
{
if (!txq->sta)
return MT_TXQ_BE;
@@ -184,7 +184,7 @@ mt76_txq_get_qid(struct ieee80211_txq *txq)
}
static struct sk_buff *
mt76_txq_dequeue(struct mt76_dev *dev, struct mt76_txq *mtxq, bool ps)
mt76x2_txq_dequeue(struct mt76x2_dev *dev, struct mt76x2_txq *mtxq, bool ps)
{
struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
struct sk_buff *skb;
@@ -207,7 +207,7 @@ mt76_txq_dequeue(struct mt76_dev *dev, struct mt76_txq *mtxq, bool ps)
}
static void
mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb)
mt76x2_check_agg_ssn(struct mt76x2_txq *mtxq, struct sk_buff *skb)
{
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
@@ -218,52 +218,52 @@ mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb)
}
static void
mt76_queue_ps_skb(struct mt76_dev *dev, struct ieee80211_sta *sta,
mt76x2_queue_ps_skb(struct mt76x2_dev *dev, struct ieee80211_sta *sta,
struct sk_buff *skb, bool last)
{
struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv;
struct mt76x2_sta *msta = (struct mt76x2_sta *) sta->drv_priv;
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
struct mt76_wcid *wcid = &msta->wcid;
struct mt76x2_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
struct mt76x2_wcid *wcid = &msta->wcid;
info->control.flags |= IEEE80211_TX_CTRL_PS_RESPONSE;
if (last)
info->flags |= IEEE80211_TX_STATUS_EOSP;
mt76_skb_set_moredata(skb, !last);
mt76_tx_queue_skb(dev, hwq, skb, wcid, sta);
mt76x2_skb_set_moredata(skb, !last);
mt76x2_tx_queue_skb(dev, hwq, skb, wcid, sta);
}
void
mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
mt76x2_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
u16 tids, int nframes,
enum ieee80211_frame_release_type reason,
bool more_data)
{
struct mt76_dev *dev = hw->priv;
struct mt76x2_dev *dev = hw->priv;
struct sk_buff *last_skb = NULL;
struct mt76_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
struct mt76x2_queue *hwq = &dev->q_tx[MT_TXQ_PSD];
int i;
for (i = 0; tids && nframes; i++, tids >>= 1) {
struct ieee80211_txq *txq = sta->txq[i];
struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
struct mt76x2_txq *mtxq = (struct mt76x2_txq *) txq->drv_priv;
struct sk_buff *skb;
if (!(tids & 1))
continue;
do {
skb = mt76_txq_dequeue(dev, mtxq, true);
skb = mt76x2_txq_dequeue(dev, mtxq, true);
if (!skb)
break;
if (mtxq->aggr)
mt76_check_agg_ssn(mtxq, skb);
mt76x2_check_agg_ssn(mtxq, skb);
nframes--;
if (last_skb) {
mt76_queue_ps_skb(dev, sta, last_skb, false);
mt76x2_queue_ps_skb(dev, sta, last_skb, false);
last_skb = skb;
}
} while (nframes);
@@ -272,17 +272,17 @@ mt76_release_buffered_frames(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
if (!last_skb)
return;
mt76_queue_ps_skb(dev, sta, last_skb, true);
mt76_kick_queue(dev, hwq);
mt76x2_queue_ps_skb(dev, sta, last_skb, true);
mt76x2_kick_queue(dev, hwq);
}
static int
mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
struct mt76_txq *mtxq, bool *empty)
mt76x2_txq_send_burst(struct mt76x2_dev *dev, struct mt76x2_queue *hwq,
struct mt76x2_txq *mtxq, bool *empty)
{
struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
struct ieee80211_tx_info *info;
struct mt76_wcid *wcid;
struct mt76x2_wcid *wcid;
struct sk_buff *skb = NULL;
int n_frames = 1, limit;
struct ieee80211_tx_rate tx_rate;
@@ -291,14 +291,14 @@ mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
int idx;
if (txq->sta) {
struct mt76_sta *sta = (struct mt76_sta *) txq->sta->drv_priv;
struct mt76x2_sta *sta = (struct mt76x2_sta *) txq->sta->drv_priv;
wcid = &sta->wcid;
} else {
struct mt76_vif *mvif = (struct mt76_vif *) txq->vif->drv_priv;
struct mt76x2_vif *mvif = (struct mt76x2_vif *) txq->vif->drv_priv;
wcid = &mvif->group_wcid;
}
skb = mt76_txq_dequeue(dev, mtxq, false);
skb = mt76x2_txq_dequeue(dev, mtxq, false);
if (!skb) {
*empty = true;
return 0;
@@ -315,9 +315,9 @@ mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
limit = ampdu ? 16 : 3;
if (ampdu)
mt76_check_agg_ssn(mtxq, skb);
mt76x2_check_agg_ssn(mtxq, skb);
idx = mt76_tx_queue_skb(dev, hwq, skb, wcid, txq->sta);
idx = mt76x2_tx_queue_skb(dev, hwq, skb, wcid, txq->sta);
if (idx < 0)
return idx;
@@ -328,7 +328,7 @@ mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
if (probe)
break;
skb = mt76_txq_dequeue(dev, mtxq, false);
skb = mt76x2_txq_dequeue(dev, mtxq, false);
if (!skb) {
*empty = true;
break;
@@ -346,9 +346,9 @@ mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
info->control.rates[0] = tx_rate;
if (cur_ampdu)
mt76_check_agg_ssn(mtxq, skb);
mt76x2_check_agg_ssn(mtxq, skb);
idx = mt76_tx_queue_skb(dev, hwq, skb, wcid, txq->sta);
idx = mt76x2_tx_queue_skb(dev, hwq, skb, wcid, txq->sta);
if (idx < 0)
return idx;
@@ -360,24 +360,24 @@ mt76_txq_send_burst(struct mt76_dev *dev, struct mt76_queue *hwq,
hwq->entry[idx].schedule = true;
}
mt76_kick_queue(dev, hwq);
mt76x2_kick_queue(dev, hwq);
return n_frames;
}
static int
mt76_txq_schedule_list(struct mt76_dev *dev, struct mt76_queue *hwq)
mt76x2_txq_schedule_list(struct mt76x2_dev *dev, struct mt76x2_queue *hwq)
{
struct mt76_txq *mtxq, *mtxq_last;
struct mt76x2_txq *mtxq, *mtxq_last;
int len = 0;
restart:
mtxq_last = list_last_entry(&hwq->swq, struct mt76_txq, list);
mtxq_last = list_last_entry(&hwq->swq, struct mt76x2_txq, list);
while (!list_empty(&hwq->swq)) {
bool empty = false;
int cur;
mtxq = list_first_entry(&hwq->swq, struct mt76_txq, list);
mtxq = list_first_entry(&hwq->swq, struct mt76x2_txq, list);
if (mtxq->send_bar && mtxq->aggr) {
struct ieee80211_txq *txq = mtxq_to_txq(mtxq);
struct ieee80211_sta *sta = txq->sta;
@@ -394,7 +394,7 @@ restart:
list_del_init(&mtxq->list);
cur = mt76_txq_send_burst(dev, hwq, mtxq, &empty);
cur = mt76x2_txq_send_burst(dev, hwq, mtxq, &empty);
if (!empty)
list_add_tail(&mtxq->list, &hwq->swq);
@@ -410,7 +410,7 @@ restart:
return len;
}
void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq)
void mt76x2_txq_schedule(struct mt76x2_dev *dev, struct mt76x2_queue *hwq)
{
int len;
@@ -418,32 +418,32 @@ void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq)
if (hwq->swq_queued >= 4 || list_empty(&hwq->swq))
break;
len = mt76_txq_schedule_list(dev, hwq);
len = mt76x2_txq_schedule_list(dev, hwq);
} while (len > 0);
}
void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq)
void mt76x2_txq_init(struct mt76x2_dev *dev, struct ieee80211_txq *txq)
{
struct mt76_txq *mtxq;
struct mt76x2_txq *mtxq;
if (!txq)
return;
mtxq = (struct mt76_txq *) txq->drv_priv;
mtxq = (struct mt76x2_txq *) txq->drv_priv;
INIT_LIST_HEAD(&mtxq->list);
skb_queue_head_init(&mtxq->retry_q);
mtxq->hwq = &dev->q_tx[mt76_txq_get_qid(txq)];
mtxq->hwq = &dev->q_tx[mt76x2_txq_get_qid(txq)];
}
void
mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta)
mt76x2_stop_tx_queues(struct mt76x2_dev *dev, struct ieee80211_sta *sta)
{
int i;
for (i = 0; i < ARRAY_SIZE(sta->txq); i++) {
struct ieee80211_txq *txq = sta->txq[i];
struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
struct mt76x2_txq *mtxq = (struct mt76x2_txq *) txq->drv_priv;
spin_lock_bh(&mtxq->hwq->lock);
mtxq->send_bar = mtxq->aggr;
@@ -453,29 +453,29 @@ mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta)
}
}
void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq)
void mt76x2_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq)
{
struct mt76_dev *dev = hw->priv;
struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
struct mt76_queue *hwq = mtxq->hwq;
struct mt76x2_dev *dev = hw->priv;
struct mt76x2_txq *mtxq = (struct mt76x2_txq *) txq->drv_priv;
struct mt76x2_queue *hwq = mtxq->hwq;
spin_lock_bh(&hwq->lock);
if (list_empty(&mtxq->list))
list_add_tail(&mtxq->list, &hwq->swq);
mt76_txq_schedule(dev, hwq);
mt76x2_txq_schedule(dev, hwq);
spin_unlock_bh(&hwq->lock);
}
void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq)
void mt76x2_txq_remove(struct mt76x2_dev *dev, struct ieee80211_txq *txq)
{
struct mt76_txq *mtxq;
struct mt76_queue *hwq;
struct mt76x2_txq *mtxq;
struct mt76x2_queue *hwq;
struct sk_buff *skb;
if (!txq)
return;
mtxq = (struct mt76_txq *) txq->drv_priv;
mtxq = (struct mt76x2_txq *) txq->drv_priv;
hwq = mtxq->hwq;
spin_lock_bh(&hwq->lock);
util.c
+2 -2
View File
@@ -13,14 +13,14 @@
#include "mt76.h"
void mt76_remove_hdr_pad(struct sk_buff *skb)
void mt76x2_remove_hdr_pad(struct sk_buff *skb)
{
int len = ieee80211_get_hdrlen_from_skb(skb);
memmove(skb->data + 2, skb->data, len);
skb_pull(skb, 2);
}
int mt76_insert_hdr_pad(struct sk_buff *skb)
int mt76x2_insert_hdr_pad(struct sk_buff *skb)
{
int len = ieee80211_get_hdrlen_from_skb(skb);
int ret;